4-to-2 Encoder Circuit Diagram

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A 4-to-2 encoder converts four mutually exclusive active-high inputs into a 2-bit binary output code, implemented with two OR gates and used in digital systems to compress data lines.

A 4-to-2 encoder is a combinational logic circuit that accepts four input lines (I0–I3) and produces two output lines (A1, A0) representing the binary code of whichever single input is asserted. The fundamental assumption is that exactly one input is active at any given time — this is the basic encoder constraint.

The truth table for a basic 4-to-2 encoder is straightforward: when I0 is high, outputs are A1=0, A0=0 (binary 00); when I1 is high, outputs are A1=0, A0=1 (binary 01); when I2 is high, outputs are A1=1, A0=0 (binary 10); when I3 is high, outputs are A1=1, A0=1 (binary 11). The Boolean expressions reduce to: A1 = I2 + I3, and A0 = I1 + I3. Each output is realised with a single 2-input OR gate, so the entire circuit requires just two OR gates.

A critical limitation of the basic encoder is that it cannot handle ambiguous states — if two inputs are simultaneously active, the output is the OR of both codes, producing an incorrect and misleading result. This limitation led to the development of the priority encoder. In an 8-to-3 or 4-to-2 priority encoder (such as the 74HC148 or 74LS148 for 8-to-3), a defined hierarchy resolves conflicts: the highest-priority active input determines the output, and a GS (Group Select) output signals that at least one input is valid. For the 4-to-2 priority variant, I3 has highest priority (overrides all), followed by I2, I1, and I0.

Practical applications include keyboard encoding, interrupt priority controllers in microprocessors, and multiplexer address generation. Encoders are also cascadable — enable (EI/EO) pins on priority encoder ICs allow multiple devices to be daisy-chained to handle larger input counts. TTL and CMOS families both offer encoder ICs; CMOS operates across a wider voltage range (2V–6V for HC series) and draws far less quiescent current than TTL.

How to wire 4 to 2 encoder circuit diagram

Identify your input and output requirements Confirm you have exactly four mutually exclusive input signals (I0–I3) and require a 2-bit binary output (A1, A0). Determine whether basic or priority encoding is needed based on whether simultaneous inputs are possible.
Write the truth table List all four valid input states in columns I3, I2, I1, I0 and their corresponding outputs A1, A0. Verify the pattern: I0→00, I1→01, I2→10, I3→11.
Derive Boolean expressions using the truth table Inspect which inputs cause each output to be high. A1 is high for I2 and I3, so A1 = I2 + I3. A0 is high for I1 and I3, so A0 = I1 + I3.
Select and connect OR gates Use two 2-input OR gates. Connect I2 and I3 to the inputs of the first gate to produce A1. Connect I1 and I3 to the inputs of the second gate to produce A0. Unused gate inputs should be tied to logic low.
Add supply decoupling Place a 100nF ceramic capacitor between VCC and GND as close as possible to each IC power pin to suppress switching noise and prevent false triggering.
Verify operation with a truth table test Apply each of the four valid input combinations one at a time (using switches or a function generator) and confirm the output LEDs or logic probe shows the correct binary code for each.
Consider invalid input handling If two inputs may be simultaneously active in your system, replace the basic encoder with a priority encoder IC or add priority logic to prevent ambiguous output codes.

Specifications

Number of inputs	4 (I0, I1, I2, I3)
Number of outputs	2 (A1 MSB, A0 LSB)
Logic gates required (basic)	2 × 2-input OR gates
Supply voltage (CMOS HC series)	2V – 6V
Supply voltage (TTL LS series)	4.75V – 5.25V
Propagation delay (HC series, typical at 5V)	~7 ns
Boolean expression A1	I2 + I3
Boolean expression A0	I1 + I3

Safety warnings

This is a low-voltage digital circuit operating at 3.3V or 5V DC — no high-voltage hazards are present, but always verify your power supply voltage matches the logic family before powering the circuit.
Never leave unused CMOS gate inputs floating; tie them to VCC or GND to prevent oscillation, excessive current draw, and potential IC damage.
Do not connect TTL outputs directly to CMOS inputs without level-shifting if operating at different supply voltages — check fan-out and voltage compatibility in the datasheet.
Discharge any static electricity by touching a grounded metal surface before handling CMOS ICs, as electrostatic discharge can permanently damage gate oxides.

Tools needed

Solderless breadboard or PCB
Digital multimeter (continuity and DC voltage measurement)
Logic probe or oscilloscope for output verification
DC bench power supply or regulated 5V USB supply
Wire strippers and jump wires
Anti-static wrist strap (recommended when handling CMOS ICs)

Common mistakes

Activating two inputs simultaneously on a basic (non-priority) encoder, which produces an incorrect output without any error flag — always use a priority encoder if simultaneous inputs are possible.
Leaving CMOS input pins floating, causing unpredictable logic levels and excessive power consumption due to the input stage biasing into the linear region.
Confusing the encoder output bit order — A1 is the most significant bit (MSB) and A0 is the least significant bit (LSB); swapping them produces codes that are mirror images of the intended values.
Forgetting that the OR gate used for A0 needs both I1 and I3 as inputs, not I1 and I2 — a common error when reading the truth table too quickly.
Omitting decoupling capacitors and then troubleshooting phantom glitches that are actually power supply noise coupling into the logic inputs.

Troubleshooting

Output remains at 00 regardless of which input is activated: Cause: OR gate inputs are not receiving the asserted signal — likely an open connection between the input switch and the gate, or the pull-down resistors are holding the signal low even when the switch is closed Fix: Use a logic probe to measure the gate input pins directly. Verify the switch wiring routes through to the correct gate input pin, and confirm pull-down resistors are connected from the input node to GND, not between the switch and the gate.
Both output bits appear always high (11): Cause: Inputs are floating or connected directly to VCC, causing all OR gates to continuously output high Fix: Add 10kΩ pull-down resistors from each input line to GND. Re-test with a single switch active at a time.
Output code is incorrect (e.g., I2 active gives 01 instead of 10): Cause: Gate connections are swapped — A1 and A0 gate inputs have been wired to the wrong input lines Fix: Cross-reference the wiring against the Boolean expressions: A1 gate inputs must be I2 and I3; A0 gate inputs must be I1 and I3. Rewire accordingly.
IC becomes hot and draws excess current: Cause: CMOS inputs are floating or operating in the linear region, or supply voltage exceeds the rated maximum for the logic family Fix: Immediately remove power. Tie all unused inputs to VCC or GND. Verify supply voltage is within the IC's absolute maximum rating before reapplying power.

Frequently asked questions

What is the difference between a basic encoder and a priority encoder?

A basic 4-to-2 encoder assumes only one input is ever active at a time and produces incorrect output if multiple inputs are asserted simultaneously. A priority encoder resolves conflicts by assigning a hierarchy to inputs, always encoding the highest-priority active input and ignoring lower-priority ones.

How many logic gates does a 4-to-2 encoder require?

The minimal implementation uses just two 2-input OR gates. Output A1 is driven by I2 OR I3, and output A0 is driven by I1 OR I3. No additional gates are needed for the basic (non-priority) version, making it extremely compact.

What is the Boolean expression for each output of a 4-to-2 encoder?

A1 (the most significant output bit) equals I2 OR I3. A0 (the least significant output bit) equals I1 OR I3. These expressions are derived directly from the truth table by identifying which input conditions cause each output to be logic high.

Can a 4-to-2 encoder be built from NAND gates only?

Yes. Any OR function can be realised using NAND gates via De Morgan's theorem: A OR B equals NAND(NOT A, NOT B), which simplifies to NAND(NAND(A,A), NAND(B,B)). This approach uses more gates but is useful when only NAND gates are available in a given logic family.

What does the enable output (EO) do on a priority encoder IC?

The Enable Output (EO) goes active when the Enable Input (EI) is active and all encoded inputs are inactive. It allows cascading multiple encoder ICs: the EO of a higher-priority device connects to the EI of a lower-priority device, extending the input count without additional logic.

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