7408 Pin Diagram – Quad 2-Input AND Gate Pinout and Wiring Guide

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The 7408 is a 14-pin DIP quad 2-input AND gate IC. Pin 7 is GND, pin 14 is VCC. This reference covers the full pinout, wiring, and practical use.

The 7408 is part of the 74xx TTL (Transistor-Transistor Logic) logic family and contains four independent 2-input AND gates in a single 14-pin dual in-line package (DIP-14). Each gate produces a HIGH output only when both of its inputs are simultaneously HIGH — the foundational AND logic function.

The pinout is standardised. Pin 7 is ground (GND) and pin 14 is the positive supply (VCC), typically 4.75 V to 5.25 V for standard 74LS08 variants or 2 V to 6 V for 74HC08 CMOS equivalents. The four gates are arranged as follows:

- Gate 1: inputs on pins 1 and 2, output on pin 3. - Gate 2: inputs on pins 4 and 5, output on pin 6. - Gate 3: inputs on pins 9 and 10, output on pin 8. - Gate 4: inputs on pins 12 and 13, output on pin 11.

Pin orientation follows standard DIP convention: pin 1 is identified by a notch or dot at one end of the package; pins count down the left side and up the right side when the notch faces left.

The 74LS08 variant is the low-power Schottky version, drawing approximately 2 mA per gate at maximum output current sink of 8 mA. The 74HC08 CMOS version operates over a wider voltage range and draws significantly less quiescent current, making it preferred in battery-powered designs.

In practical circuits, the 7408 is used for enable/disable logic, signal gating, address decoding in combination with other gates, and interlock circuits where two conditions must be simultaneously true before an action is permitted — such as a safety interlock requiring both a key signal and an enable signal before activating a relay driver.

Unused inputs must never be left floating in TTL variants; tie them HIGH (to VCC through a 1 kΩ resistor) or LOW (to GND) to prevent erratic switching from ambient noise pickup. CMOS variants are even more sensitive to floating inputs and can latch up or draw excessive current if inputs are left unconnected.

How to wire 7408 pin diagram

Identify pin 1 Locate the notch or circular indent at one end of the DIP package. With the notch facing left, pin 1 is the bottom-left pin. All pin numbers increase down the left side and then up the right side.
Connect power and ground Connect pin 14 (VCC) to your 5 V regulated supply rail. Connect pin 7 (GND) to the common ground. Add a 100 nF ceramic decoupling capacitor between VCC and GND, placed as close to the IC body as possible, to suppress switching noise.
Wire the inputs for the gate you need Choose one of the four gates. For Gate 1, connect your two logic-level input signals to pins 1 and 2. Ensure both signals are within the valid logic level range: below 0.8 V for LOW, above 2.0 V for HIGH (74LS08 thresholds).
Connect the output Connect pin 3 (Gate 1 output) to your load — whether a subsequent logic gate input, a transistor base driver, or a low-current LED with series resistor. Do not exceed the fan-out current rating.
Handle unused gates Tie unused input pins to GND (for LOW) or VCC through a 1 kΩ resistor (for HIGH). Leave corresponding outputs unconnected. Do not leave inputs floating.
Verify logic function on bench Apply the four possible input combinations (00, 01, 10, 11) and measure the output. Only the 11 combination should produce a HIGH output. Use a logic probe or multimeter in DC voltage mode.
Check thermal and loading conditions Measure supply current with all four gates switching. If the IC runs warm, verify decoupling is adequate and that no output is short-circuited. The 7408 has no thermal shutdown; sustained overload will damage the die.

Specifications

Package	DIP-14 (also available in SOIC-14, TSSOP-14)
Supply voltage (74LS08)	4.75 V to 5.25 V
Supply voltage (74HC08)	2.0 V to 6.0 V
VCC pin	Pin 14
GND pin	Pin 7
Number of gates	4 (quad)
Gate inputs	2 per gate
Output current sink (74LS08 IOL)	8 mA maximum
Propagation delay (74LS08)	Approximately 10 ns typical

Safety warnings

The 7408 operates at low voltages (5 V or less) and presents no significant shock hazard under normal use. However, always power off the circuit before inserting or removing the IC to prevent electrostatic discharge (ESD) damage or latch-up on CMOS variants.
CMOS variants (74HC08) are sensitive to ESD. Handle using anti-static precautions: use an ESD wrist strap, work on an anti-static mat, and store the IC in anti-static packaging.
Do not exceed the absolute maximum ratings. VCC above 7 V on most variants will permanently damage the IC. Reverse polarity on the supply will also destroy the device.
Never short-circuit an output to VCC or GND while the device is powered. TTL outputs sourcing into a short will overheat rapidly and fail.

Tools needed

Multimeter (DC voltage range)
Logic probe (optional but useful for fast switching signals)
Breadboard or PCB with appropriate IC socket
Wire strippers and jumper wires
Anti-static wrist strap and mat (especially for 74HC08 CMOS variant)
Oscilloscope (optional, for verifying signal timing at higher frequencies)

Common mistakes

Leaving input pins floating — always tie unused inputs to a defined logic level.
Connecting the IC backwards — always locate pin 1 via the notch or dot before wiring.
Omitting the decoupling capacitor — without it, switching noise causes erratic behaviour on sensitive boards.
Exceeding fan-out — driving too many TTL inputs from a single 7408 output causes voltage levels to collapse below the HIGH threshold.
Using a 74HC08 with 5 V inputs when powered at 3.3 V — the input voltage would exceed VCC, violating absolute maximum ratings and risking latch-up.
Confusing the 7408 (AND) with the 7432 (OR) or 7400 (NAND) — verify the part number before soldering.

Troubleshooting

Output stays LOW regardless of inputs: Cause: GND or VCC connection missing, or the IC is inserted backwards Fix: Verify pin 7 is at 0 V and pin 14 is at 5 V with a multimeter. Check pin 1 orientation against the package notch.
Output is erratic or oscillates with stable inputs: Cause: Missing decoupling capacitor allowing supply noise to couple into the gate Fix: Add a 100 nF ceramic capacitor between VCC and GND as close to the IC as possible. Check that ground return paths are low impedance.
IC becomes hot within seconds of power-on: Cause: Latch-up (74HC08) caused by floating inputs or input voltage exceeding VCC, or a shorted output Fix: Power off immediately. Verify all input voltages are within 0 V to VCC range. Tie all unused inputs to a defined level. Check for wiring shorts.

Frequently asked questions

What is the supply voltage for the 7408 IC?

The standard 74LS08 variant requires 4.75 V to 5.25 V (nominally 5 V). The 74HC08 CMOS equivalent operates from 2 V to 6 V, making it suitable for 3.3 V and 5 V systems alike.

Which pin is GND on the 7408?

Pin 7 is GND. Pin 14 is VCC. This is consistent across all 7408 package variants including DIP-14 and SOIC-14.

How many AND gates are inside the 7408?

The 7408 contains four independent 2-input AND gates. Each gate has its own pair of inputs and a dedicated output, making all four usable simultaneously in the same circuit.

What happens if I leave an input pin floating on a 7408?

On TTL variants, a floating input may read HIGH due to the internal transistor structure, but this is unreliable and noise-sensitive. On CMOS (74HC08), floating inputs can cause latch-up and excessive current draw. Always tie unused inputs to VCC or GND.

Can the 7408 drive an LED directly?

The 74LS08 can sink up to 8 mA, which is sufficient to drive a low-current LED connected between VCC and the output (with an appropriate series resistor). The LED should be connected so the output sinks current. Check your specific variant's datasheet for exact IOL and IOH limits.

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