Common Emitter Amplifier Circuit Diagram
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A common emitter (CE) amplifier circuit diagram shows an NPN BJT with the emitter terminal common to both the input and output signal paths, the base as the input, and the collector as the output. The CE configuration provides both voltage gain and current gain, making it the most widely used single-transistor amplifier stage. The output signal is 180° out of phase with the input.
The common emitter amplifier is the fundamental BJT amplifier configuration. In the standard circuit, a voltage divider (R1 and R2) from VCC to GND biases the base, setting the quiescent operating point (Q-point). The collector resistor RC converts the collector current variations into voltage changes. An emitter resistor RE stabilises the Q-point against transistor parameter variations and temperature. Coupling capacitors (Cin and Cout) block DC and pass AC signals.
Voltage divider biasing: R1 and R2 set the base voltage: VB = VCC × R2/(R1+R2). The emitter voltage is VE = VB − 0.7 V. The quiescent emitter current IC ≈ IE = VE/RE. The collector voltage VC = VCC − IC×RC. For linear amplification, set VC ≈ VCC/2 (midpoint bias) to allow maximum output swing.
Small-signal voltage gain: The small-signal emitter resistance is re = 26 mV / IC (in milliamps at room temperature). Without emitter bypass capacitor: Av = −RC / (re + RE). With emitter bypass capacitor (CE across RE): Av = −RC / re. The negative sign indicates phase inversion.
Example: VCC = 12 V, IC = 2 mA, RC = 3 kΩ, RE = 1 kΩ. - re = 26/2 = 13 Ω - Av (unbypassed) = −3000/(13+1000) ≈ −2.96 (very low, stable) - Av (bypassed) = −3000/13 ≈ −231 (high gain)
Current gain: Ai = −β (approximately equal to hFE). Input resistance: Rin = R1||R2||(β × re) for bypassed emitter, or R1||R2||(β×(re+RE)) without bypass.
Output resistance: Rout ≈ RC (for ideal transistor; in practice, slightly less due to the Early effect output resistance ro ≈ VA/IC where VA is the Early voltage).
Frequency response: The CE amplifier's bandwidth is limited at low frequencies by the coupling and bypass capacitors, and at high frequencies by transistor transition frequency fT and Miller effect. The lower cutoff frequency fL is set by the largest of the RC time constants formed by Cin, Cout, and CE. The upper cutoff frequency fH is limited by the transistor's fT (e.g. 300 MHz for 2N2222) divided by the closed-loop gain.
Miller effect: The feedback capacitance Cμ between base and collector is amplified by the Miller factor (1 + |Av|), creating an equivalent input capacitance of Cμ × (1 + |Av|). This significantly reduces the high-frequency bandwidth when Av is large.
Emitter bypass capacitor CE: CE is placed across RE to short-circuit RE at AC frequencies. The lower cutoff due to CE is fCE = 1/(2π × CE × (RE||(re + RS/β))), where RS is the source resistance. CE must be large enough to have low reactance at the lowest frequency of interest.
Design guidelines for bias stability: The design rule is that the current through the voltage divider (VCC/(R1+R2)) should be at least 10× the base current IB = IC/β. This makes the base voltage stiff (relatively independent of transistor β variations). For RE, choosing RE = RC/3 to RC/4 provides good bias stability.
Common part: 2N2222 (NPN, fT = 300 MHz, IC_max = 600 mA), BC547 (NPN, fT = 300 MHz, IC_max = 100 mA), 2N3904 (NPN, fT = 300 MHz, IC_max = 200 mA).
Build and simulate a common emitter amplifier in the free circuit diagram editor at circuitdiagrammaker.com — place an NPN BJT, add biasing resistors, RC, RE, CE, and coupling capacitors, then trace the voltage gain across frequency.
How to wire common emitter amplifier circuit diagram
- Set the quiescent collector current Choose IC (e.g. 1–2 mA) based on desired gain and power consumption. Lower IC gives higher re and lower gain; higher IC gives lower re and higher gain.
- Choose RC and RE Set VC ≈ VCC/2 for maximum output swing: RC = (VCC/2 − VCE_min)/IC ≈ VCC/(2×IC). Choose RE ≈ RC/4 for bias stability.
- Calculate bias resistors R1 and R2 VB = VE + 0.7 = IC×RE + 0.7. Then R2 = VB × 10/IC_divider and R1 = (VCC−VB)/IC_divider, where IC_divider = IC/β × 10 to ensure stiff bias.
- Select the transistor Choose an NPN transistor (e.g. 2N2222) with IC_max and VCEO exceeding the design by 2×, and verify β is in range at the chosen IC using the datasheet.
- Add coupling capacitors Cin and Cout Choose Cin and Cout so their reactance XC < 0.1 × Rin (or Rout) at the lowest operating frequency. Cin = 1/(2πfL × Rin/10), typically 1–10 μF.
- Add emitter bypass capacitor CE CE shorts RE at AC: CE ≥ 10/(2πfL × RE). For fL = 20 Hz and RE = 1 kΩ: CE ≥ 10/(2π×20×1000) ≈ 80 μF → use 100 μF electrolytic.
- Verify and measure AC voltage gain Apply a small AC signal (e.g. 10 mV peak at 1 kHz) to the input through Cin. Measure output voltage. Av = Vout/Vin. Compare with −RC/re.
Specifications
| Small-signal emitter resistance | re = 26 mV / IC(mA) Ω |
|---|---|
| Voltage gain (bypassed RE) | Av = −RC / re |
| Voltage gain (unbypassed RE) | Av = −RC / (re + RE) |
| Input resistance (bypassed) | Rin = R1||R2||(β×re) |
| Output resistance | Rout ≈ RC |
| Phase shift (CE amp) | 180° (output inverted relative to input) |
| Bias point (voltage divider) | VB = VCC × R2/(R1+R2); VC ≈ VCC/2 for max swing |
| Stability rule for bias divider | I_divider ≥ 10 × IB = 10 × IC/β |
| Common transistors | 2N2222, BC547, 2N3904 (NPN) |
| Typical quiescent IC | 0.5 mA – 5 mA for small-signal stages |
Safety warnings
- Keep the quiescent collector current below the transistor's IC_max rating — operating near the limit causes excessive heating and reduces transistor lifespan.
- Polarised electrolytic capacitors (Cin, Cout, CE) must be installed with the correct polarity; positive terminal to the higher DC voltage node to prevent gas build-up and rupture.
Tools needed
- NPN transistor (2N2222, BC547, or 2N3904)
- Resistors R1, R2, RC, RE (values from design calculation)
- Electrolytic capacitors Cin, Cout, CE (from frequency requirement)
- DC regulated power supply (9 V or 12 V)
- Oscilloscope (to measure gain and waveform quality)
- Signal generator (1 kHz test tone)
Common mistakes
- Forgetting the emitter bypass capacitor CE, which leaves RE in the AC signal path and severely reduces the voltage gain to RC/(re+RE) instead of RC/re.
- Setting VC = VCC instead of VCC/2 — the transistor is biased at saturation edge, clipping positive signal peaks immediately.
- Using too small coupling capacitors so their reactance is significant at the signal frequency, attenuating the input and output.
- Ignoring transistor β variation — designing for a nominal β without checking that the biasing works for the minimum β in the production tolerance range.
Troubleshooting
- Amplifier clips output waveform even for small inputs
- Cause: Q-point is not at mid-supply; collector voltage is too close to VCC or to GND. Fix: Measure VCE statically. Adjust R1/R2 ratio to bring VC closer to VCC/2 for maximum linear swing.
- Voltage gain is much lower than calculated
- Cause: Emitter bypass capacitor CE is missing or too small, leaving RE in the AC path. Fix: Verify CE is installed across RE and measure its capacitance. At the test frequency, XCE should be < 0.1 × RE.
- Amplifier oscillates or produces high-frequency ringing
- Cause: Layout stray inductance or capacitance is causing positive feedback at high frequency. Fix: Add a small base resistor (100 Ω – 1 kΩ) in series with the base to damp the oscillation. Keep supply bypassing (100 nF) close to VCC pin.
Frequently asked questions
What is the voltage gain of a common emitter amplifier circuit diagram?
The voltage gain is Av = −RC/re when the emitter bypass capacitor is present, where re = 26mV/IC. The negative sign indicates 180° phase inversion. Without the bypass capacitor, Av = −RC/(re+RE), which is much smaller but more stable.
Why is the output of a common emitter amplifier inverted?
When the base voltage rises, the transistor conducts more, increasing the collector current. The increased current through RC drops more voltage across RC, pulling the collector voltage down. This gives an inverse relationship between Vin and Vout — a 180° phase shift.
What is the purpose of the emitter bypass capacitor in a CE amplifier?
The emitter bypass capacitor CE is connected across RE. At DC and low frequencies, CE has high impedance and RE provides negative feedback, stabilising the bias. At signal frequencies, CE has low impedance, effectively shorting RE from the AC signal path and allowing full gain Av = −RC/re.
Why is voltage divider biasing used in a common emitter amplifier?
Voltage divider biasing (R1 and R2) sets a stable base voltage VB that is relatively independent of transistor β variations. By making the divider current much larger than the base current (≥10×IB), the Q-point remains stable across transistor production spread and temperature changes.
How does the common emitter amplifier compare to common base and common collector?
The CE amplifier provides both voltage gain (>1) and current gain (≈β) with 180° phase inversion. The common base gives voltage gain but current gain < 1 with no phase inversion. The common collector (emitter follower) gives voltage gain ≈ 1 with high current gain and no phase inversion. CE is the most used for voltage amplification.
What IC or transistor is used for a common emitter amplifier?
Common choices are 2N2222 (600 mA, 40 V, fT=300 MHz), BC547 (100 mA, 45 V, fT=300 MHz), and 2N3904 (200 mA, 40 V, fT=300 MHz). For higher frequency applications, BFR93 or BFR520 RF transistors are used. The choice depends on the required frequency, gain, and current.
What limits the high-frequency performance of a CE amplifier?
The Miller effect multiplies the base-collector capacitance Cμ by (1 + |Av|), creating a large effective input capacitance that forms a low-pass filter with the source resistance. At frequencies approaching fT/|Av|, gain starts falling. Using a cascode configuration eliminates the Miller effect and extends bandwidth.
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