Ladder Diagram Simulator: Simulate PLC Ladder Logic Free in Your Browser
This is a free printable ladder diagram simulator: download the diagram as SVG or open it and print to paper or PDF.
A ladder diagram simulator lets you write, run, and debug PLC ladder logic programs without physical hardware — directly in a web browser. circuitdiagrammaker's free online ladder diagram tool runs a full PLC scan cycle in the browser, lets you force input bits on and off, and highlights every rung state in real time, so you can validate your logic before you touch a real panel.
What does a ladder diagram simulator actually do? At its core it replicates the four-phase PLC scan cycle: it reads all input states into an input image table, executes every rung of ladder logic from top to bottom, writes the resulting output states to an output image table, then repeats — continuously, just as a hardware PLC does. Because the scan runs in software, you can pause it, single-step rung by rung, or accelerate time to skip through timer presets that would take ten seconds on real hardware.
The biggest advantage of an online simulator over desktop PLC software is accessibility. Traditional environments like Allen-Bradley Studio 5000 or Siemens TIA Portal require a Windows PC, licence fees, and often a physical PLC or simulator dongle to do more than edit code. A browser-based ladder diagram simulator has none of those barriers — open a URL and you are writing and running ladder logic within thirty seconds.
For students, the no-download angle is especially valuable. College lab sessions are time-limited; spending twenty minutes installing and licencing software before you can type a single rung is wasteful. An online tool means every student in the room is at the same starting point instantly. For trainers, it means exercises can be assigned as homework on any device — Windows, macOS, Chromebook, or tablet.
For practising engineers the simulator serves a different purpose: rapid prototyping. When a machine has a new interlock requirement, sketching the rung logic in a simulator and verifying it with forced inputs takes five minutes. That is far quicker than uploading to a physical PLC, toggling field wiring, and downloading again. It is also safer — there is no risk of accidentally energising a motor contactor during logic development.
How forcing inputs works in a ladder diagram simulator: each input bit (I0.0, I0.1 in Siemens notation; I:0/0, I:0/1 in Allen-Bradley notation) can be toggled to TRUE or FALSE regardless of what any physical sensor would report. This lets you exercise every branch of your logic — including the rare fault branches that might not occur in normal operation for weeks. Forced outputs let you verify that the downstream wiring responds correctly before the control logic is finalised.
Online scan cycle visibility is the other killer feature. Rungs that are energised (evaluate to TRUE) are highlighted — typically in green — while de-energised rungs stay grey. Timer and counter accumulated values update on screen in real time. This visual feedback makes it immediately obvious why a rung is not energising: you can trace the logic left to right along the rail and see exactly which contact is blocking current flow.
The circuitdiagrammaker ladder diagram editor goes further by letting you export your finished program as a clean SVG or PDF. This is important for documentation: IEC 62061 and ISO 13849 machine safety documentation, panel builders' shop drawings, and maintenance manuals all require readable ladder diagrams. Generating those from the same environment where you simulated the logic eliminates transcription errors.
For a sister experience focused on full PLC simulation with multiple program organisation units (POUs), timer presets, force tables, and cross-reference lists, the companion PLC simulator at circuitdiagrammaker extends the browser-based environment with hardware-neutral execution compatible with IEC 61131-3 structured programs. You can build the logic in the ladder editor, verify the rung-by-rung behaviour, then move to the PLC simulator when you need multi-rung program execution with realistic scan timing.
Common use cases for a free online ladder diagram simulator include: learning ladder logic from scratch without buying PLC hardware; completing coursework and lab assignments; preparing for PLC technician certification exams (such as those from NPTC, ISA, or SAIT); prototyping a new machine sequence for a capital project; creating training exercises for maintenance technicians; and documenting existing programs by rebuilding and exporting them as print-quality diagrams.
Open the circuitdiagrammaker ladder diagram simulator now — it is free, runs in any modern browser, and requires no account to start building your first rung.
How to wire ladder diagram simulator
- Open the simulator Navigate to circuitdiagrammaker.com and select the Ladder Diagram tool. No login or download is required. The editor opens with a blank rung between two vertical power rails.
- Define your I/O addresses Click an empty contact on the rung and assign it an address such as I0.0 (Siemens style) or I:0/0 (Allen-Bradley style). Label it with the field device name — for example 'Start_PB' — so your program is self-documenting from the first rung.
- Build your ladder rungs Add normally open (XIC) contacts in series for AND logic, or branch them in parallel for OR logic. Add normally closed (XIO) contacts for NOT logic or interlock conditions. Place an output coil (OTE) at the right end of each rung to represent the controlled device.
- Add timers and counters Insert a TON (on-delay) or TOF (off-delay) instruction block on a rung. Enter the preset time value. The accumulated value register (ACC) will increment in real time during simulation, letting you confirm the delay works before connecting real hardware.
- Run the simulation Press the Run/Play button to start the scan cycle. The simulator begins executing rungs continuously from top to bottom. Energised rungs highlight in green; de-energised rungs stay grey.
- Force inputs to test all branches Click any input contact to toggle it ON or OFF regardless of its default state. Force each input TRUE and FALSE in turn and observe which rungs energise. Check that your stop (NC) and E-stop conditions de-energise the output correctly.
- Watch timer and counter values Observe the ACC value on timer and counter blocks incrementing in real time. Confirm that the output bit activates exactly when ACC reaches the PRE value, and resets correctly when the enable condition clears.
- Single-step the scan cycle Use the Step button to advance exactly one scan at a time. This is invaluable for debugging one-shot (OSR) instructions or transient pulse outputs that might otherwise be invisible at full scan speed.
- Export and document Once logic is validated, use the Export button to download the diagram as SVG or PDF. The exported file is print-ready for inclusion in panel drawings, functional design specifications, or maintenance manuals.
Specifications
| Deployment | Browser-based — no download or installation |
|---|---|
| Supported OS / devices | Windows, macOS, Linux, ChromeOS, iOS, Android (any modern browser) |
| Cost | Free |
| Login required | No |
| PLC language standard | IEC 61131-3 Ladder Diagram (LD) |
| Input contacts | XIC (normally open), XIO (normally closed) |
| Output instructions | OTE (energise), OTL (latch), OTU (unlatch) |
| Timer instructions | TON (on-delay), TOF (off-delay) |
| Counter instructions | CTU (count-up), CTD (count-down) |
| Comparison instructions | GEQ, LEQ, EQU, NEQ |
| Scan cycle simulation | Continuous, single-step, and paused modes |
| Input forcing | Force any input bit TRUE or FALSE during run mode |
| Online monitoring | Energised rungs highlighted in real time; ACC values displayed live |
| Export formats | SVG, PDF |
| Max rungs per program | No hard limit (browser memory dependent) |
| Address notation | Configurable (Siemens Ix.x/Qx.x or Allen-Bradley I:x/x O:x/x style) |
Safety warnings
- A simulator validates logic behaviour only — it cannot detect wiring errors, incorrect input module assignments, or misconfigured hardware parameters. Always commission on real hardware before powering a machine.
- Never use simulator output as a substitute for functional safety analysis (FMEA, HAZOP, or IEC 62061 / ISO 13849 SIL/PLe assessment) on safety-critical systems.
- E-stop and safety relay circuits must be verified with certified PLC software and physical proof-testing; browser simulator results are not acceptable as evidence for CE marking or machine safety certification.
- Force-enabling outputs in a simulator is harmless; attempting the same force on a live PLC connected to real machinery can cause unexpected motion or energisation. Always ensure the machine is in a safe state before forcing outputs on live hardware.
Tools needed
- Modern web browser (Chrome 90+, Firefox 88+, Edge 90+, or Safari 15+)
- circuitdiagrammaker.com ladder diagram editor (free, browser-based)
- I/O allocation table (spreadsheet or paper) listing all input and output addresses before building rungs
- Timer preset values for any TON/TOF instructions (derived from machine timing requirements)
- PDF viewer or SVG-capable software for reviewing exported diagrams
Common mistakes
- Forgetting to assign an address to every contact before running — unaddressed contacts default to FALSE and the rung will never energise
- Using the same output address on two separate OTE coils — the second coil's evaluation overwrites the first each scan, creating unpredictable behaviour identical to real PLC duplicate-coil bugs
- Testing only the normal-run path and never forcing the stop or E-stop condition — always verify that the NC stop contact correctly breaks the rung
- Setting timer presets to zero during testing and then forgetting to restore correct values before export — always check PRE values before generating the final documentation export
- Assuming simulator timing is cycle-accurate — browser-based simulators introduce small timing jitter; do not rely on them for sub-10 ms timing validation
Troubleshooting
- Rung stays grey (de-energised) even though the input appears to be forced TRUE
- Cause: A second contact on the same rung is still FALSE, or the contact is configured as XIO (NC) and the bit is TRUE — which correctly blocks the rung Fix: Hover over each contact to inspect its current bit value and contact type. Check every contact in series on the rung. Confirm XIC vs XIO assignment matches your intended logic.
- Output coil energises and immediately de-energises (flickers) during simulation
- Cause: The output coil bit is also used as a contact in the same rung without a seal-in branch, creating a race condition each scan Fix: Add a parallel seal-in contact (XIC using the output address) in parallel with the start contact. This latches the output once it energises.
- TON timer accumulated value never reaches the preset value
- Cause: The rung enabling the TON is de-energising before the timer completes, resetting ACC to zero on each scan Fix: Check that the rung condition enabling the timer holds TRUE continuously for the full preset duration. Add a seal-in contact if the enable condition is only a momentary pulse.
- Export produces a blank PDF
- Cause: Browser pop-up blocker is preventing the PDF window from opening, or the diagram canvas contains only unaddressed (placeholder) rungs Fix: Allow pop-ups for the site in browser settings. Ensure at least one rung has addressed contacts and a coil before exporting.
- Simulation runs but contact states do not update visually
- Cause: The browser tab has lost focus or the rendering loop has stalled Fix: Click back into the simulator canvas to restore focus. If the issue persists, refresh the page and reload the saved program.
- Counter (CTU) never resets between simulation runs
- Cause: There is no reset rung — a RES (reset) or CTD instruction tied to a reset condition is missing from the program Fix: Add a rung with a XIC contact on your reset bit driving a RES instruction targeting the counter. Force the reset bit TRUE to verify the ACC returns to zero.
Frequently asked questions
What is a ladder diagram simulator?
A ladder diagram simulator is software that executes PLC ladder logic programs without physical hardware. It replicates the PLC scan cycle — reading inputs, executing rungs, writing outputs — in software so you can verify logic, force inputs, and observe rung states before connecting to a real machine.
Is circuitdiagrammaker's ladder diagram simulator free?
Yes. The browser-based ladder diagram editor and simulator at circuitdiagrammaker.com is free to use with no download, no software installation, and no login required to start building rungs.
Can I use an online ladder diagram simulator without installing anything?
Yes. A browser-based simulator runs entirely in the browser using JavaScript and WebAssembly. Any modern browser on Windows, macOS, Linux, or a Chromebook will work. There is nothing to install.
What PLC programming instructions does the simulator support?
The circuitdiagrammaker simulator supports the core IEC 61131-3 ladder instructions: XIC (NO contact), XIO (NC contact), OTE (output coil), OTL/OTU (latch/unlatch), TON, TOF, CTU, CTD, and comparison instructions (GEQ, LEQ, EQU). See the specifications table for the full feature list.
How do I force an input in the ladder diagram simulator?
Click directly on an input contact in the simulator's run mode. A toggle or force panel appears, allowing you to set the bit to TRUE or FALSE independently of any physical input. This lets you test every logical branch including fault conditions.
Can I simulate timers without waiting for the real time to elapse?
Some simulators include a time-acceleration feature that multiplies the internal clock so a 30-second timer preset completes in 1-2 seconds of real time. The circuitdiagrammaker editor allows you to adjust timer presets directly while the simulation is running.
Is an online ladder diagram simulator good enough for professional use?
For logic validation, documentation, and training, yes. For final commissioning of safety-rated systems you will still need manufacturer-certified software (TIA Portal, Studio 5000). The online tool is ideal for design, review, and prototyping phases.
What is the difference between a ladder diagram simulator and a PLC emulator?
A simulator models the logic behaviour of a PLC program. An emulator attempts to replicate the exact instruction set and timing of a specific PLC CPU. For most programming and training purposes a simulator is sufficient; an emulator is needed only when testing firmware-specific timing or undocumented instruction behaviour.
Can I use the simulator on a tablet or Chromebook?
Yes. Because the tool runs in a browser it works on any device with a modern browser, including iPads, Android tablets, and Chromebooks. Touch-screen interaction is supported for drag-and-drop rung building.
What can I export from the ladder diagram simulator?
You can export your ladder program as an SVG vector graphic or PDF document. Both formats are print-ready at any scale and suitable for inclusion in IEC documentation, panel shop drawings, or training handouts.