Encoder Circuit Diagram: Priority Encoder Logic, Truth Table, IC Pinout and Design

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An encoder circuit diagram shows how multiple input lines are compressed into a binary output code, with a priority encoder ensuring the highest-priority active input always determines the output.

In digital electronics, an encoder is a combinational logic circuit that converts one of several active input lines into a binary output code representing that input's position or identity. The encoder reduces the number of lines required to transmit or process information — eight distinct input lines, for example, are encoded into a three-bit binary output, since 2³ = 8 possible states.

The simplest encoder is the 4-to-2 encoder: it has four input lines (I0 through I3, representing decimal values 0–3) and produces a two-bit binary output (A1 A0). Under normal operation, exactly one input line is asserted at a time, and the output is the binary code of that input's index. The Boolean expressions for a basic 4-to-2 encoder are: A1 = I2 + I3 (A1 is high when input 2 or input 3 is active); A0 = I1 + I3 (A0 is high when input 1 or input 3 is active). These are implemented directly with two two-input OR gates.

The limitation of a basic encoder becomes apparent when more than one input is asserted simultaneously: the outputs may produce an incorrect or undefined code. This is where the priority encoder solves a real problem. A priority encoder assigns a priority ranking to its inputs — typically the highest-numbered (or highest-indexed) active input takes precedence — and always encodes that input's index, regardless of which lower-priority inputs are also active. It also provides an Enable Output (EO) or Group Select (GS) signal to indicate that at least one input is active, and a Valid Output (V) to confirm the output code is meaningful.

The 74HC148 (and its TTL equivalent, the 74LS148) is the standard eight-to-three-line priority encoder IC. It has eight active-low inputs (I0–I7), three active-low binary outputs (A0–A2), a group select output (GS — active low when any input is asserted), an enable output (EO — active low when enabled and no input is active), and an enable input (EI — active low). The active-low convention means the IC logic operates inverted from a positive-logic description, which is a common point of confusion when reading the truth table.

Priority encoders are used in interrupt controllers (determining which of several pending interrupts has the highest priority), keyboard encoders (assigning a code to the pressed key), and data multiplexing applications where multiple sources compete for a shared output.

How to wire encoder circuit diagram

Define the encoder's input and output requirements Determine the number of input lines (n) and calculate the number of output bits required: output bits = ceil(log₂ n). For 4 inputs, 2 bits suffice (2² = 4). For 8 inputs, 3 bits (2³ = 8). For 9–16 inputs, 4 bits. Decide whether priority encoding is required based on whether simultaneous inputs are possible.
Draw the truth table For a 4-to-2 encoder, list all valid input combinations (one input asserted at a time for basic; all 16 input combinations for priority). For each row, determine the expected A1 and A0 output. For a priority encoder, the highest-indexed asserted input determines the output regardless of other inputs. The truth table is the specification the logic must implement.
Derive Boolean expressions using the truth table Extract the Boolean expressions for each output from the truth table using a sum-of-minterms (SOP) or Karnaugh map (K-map) simplification. For the 4-to-2 basic encoder: A1 = I2 + I3; A0 = I1 + I3. For a priority encoder, additional AND-gate and inverter logic is needed to suppress lower-priority inputs.
Implement with logic gates or select an encoder IC For small custom encoders, draw the circuit using AND, OR, and NOT gates from the derived Boolean expressions. For standard 8-to-3 priority encoding, use a 74HC148 IC, which contains the full priority logic in a single 16-pin package. Consult the IC datasheet for the pinout, active logic levels (most pins are active-low on the 74HC148), and electrical specifications.
Connect the enable input and manage the group select output For a standalone 74HC148, tie the enable input (EI) to logic low (active-low = enabled). In cascaded configurations, connect EO from the higher-priority device to EI of the lower-priority device. Connect the GS output to the upstream circuit to indicate valid output. A GS high (inactive for 74HC148) means no inputs are asserted — the output code is 111 (all outputs high, active-low) in this state.
Verify with a simulation or test circuit Before committing to PCB, verify the encoder logic using a digital logic simulator or a breadboard prototype with LED indicators on each output and GS. Apply each single input in sequence and verify the correct binary code appears on the outputs. Then apply multiple simultaneous inputs and confirm the highest-priority input determines the output while GS remains active.

Specifications

74HC148 supply voltage range	2.0–6.0 V DC
74HC148 input logic threshold (VIL max at 5 V VCC)	≤ 1.35 V (logic low recognised)
74HC148 input logic threshold (VIH min at 5 V VCC)	≥ 3.15 V (logic high recognised)
74HC148 propagation delay (typical at 5 V, 25 °C)	Approximately 10–20 ns (verify with datasheet for specific package and load)
74HC148 quiescent supply current (ICC)	Typically 80 µA maximum (CMOS quiescent — rises with switching frequency)
4-to-2 basic encoder gate count	2 × two-input OR gates (A1 = I2 + I3; A0 = I1 + I3)
Number of output bits for n inputs	Output bits = ⌈log₂(n)⌉ — e.g. 4 inputs → 2 bits; 8 inputs → 3 bits; 16 inputs → 4 bits
74HC148 package options	16-pin DIP (through-hole), 16-pin SOIC or SSOP (surface-mount)

Safety warnings

CMOS logic ICs (74HC series) are sensitive to electrostatic discharge (ESD). Handle on an anti-static mat and wear a grounded wrist strap when inserting or removing ICs from a circuit board or socket.
Do not exceed the IC's absolute maximum supply voltage (7 V for 74HC148). Overvoltage permanently destroys CMOS devices.
Floating input pins on CMOS ICs must be tied to a defined logic level (high or low) using pull-up or pull-down resistors. Floating CMOS inputs oscillate unpredictably, consume excessive current, and can permanently damage the IC.
The 74LS148 (TTL variant) requires a 5 V ±5% supply. Substituting a 74HC148 in a TTL circuit is generally acceptable but verify logic threshold compatibility with connected devices.
In prototype circuits, verify supply polarity before applying power. Reversing VCC and GND destroys CMOS and TTL ICs immediately.

Tools needed

Digital logic simulator (for truth table verification before building)
Breadboard and jumper wires (for prototype assembly)
Digital multimeter (DC voltage measurement and continuity testing)
Logic probe or oscilloscope (for verifying logic levels and signal timing)
Anti-static mat and wrist strap (ESD protection for IC handling)
IC extraction tool (for removing DIP ICs from sockets without bending pins)
Soldering iron and solder (for PCB implementation)

Common mistakes

Forgetting that the 74HC148 uses active-low logic: an output code of '000' (all outputs low) does NOT mean input 0 is selected — it means input 7 (highest priority) is active. The outputs are inverted from what a positive-logic truth table suggests.
Leaving input pins unconnected (floating) on the 74HC148, which causes erratic output behaviour. All unused inputs must be pulled high (tied to VCC through a 10 kΩ resistor) to hold them inactive in the active-low convention.
Neglecting the decoupling capacitor on the VCC pin — in digital circuits with fast edge rates, supply noise causes logic errors that are difficult to diagnose. Always place a 100 nF ceramic capacitor adjacent to every logic IC supply pin.
Confusing the 74HC148's EO and GS outputs. EO goes low when the IC is enabled AND no inputs are active (idle, output code = 111). GS goes low when the IC is enabled AND at least one input is active (valid code present). These serve opposite purposes in cascaded encoder designs.
Implementing a basic (non-priority) encoder and then applying multiple simultaneous inputs — the OR-gate-only design will produce incorrect output codes under this condition. If simultaneous inputs are possible, a priority encoder design is required.

Troubleshooting

Output code does not change when inputs are applied: Cause: Enable input (EI) is not asserted (not pulled low); VCC supply absent or incorrect; incorrect input logic level applied (active-low inputs require a low, not a high, to activate) Fix: Confirm EI is connected to logic low (for always-enabled operation). Measure VCC at the IC supply pin. Measure the input voltage on an active input — it should be near 0 V (logic low) for the 74HC148. If inputs are driven high (≈ VCC) and no pull-down is present, the inputs are all inactive and the output will remain at 111 (all outputs high).
Output is always 000 regardless of inputs: Cause: In the active-low 74HC148 context, all outputs low means input I7 is being asserted, even without intentional input. A floating or partially grounded I7 pin may be pulling the output to 000. Alternatively, GS output may be confirming the output is valid, indicating I7 is genuinely active. Fix: Measure the voltage at input pin I7. It should be near VCC (logic high, inactive) when I7 is not supposed to be asserted. If it is floating or near 0 V without an external signal, add a 10 kΩ pull-up resistor from I7 to VCC.
Priority encoder produces incorrect output when only one input is asserted: Cause: Power supply noise causing glitches on other input lines; incorrect connection of input lines to physical inputs on the IC; active-low logic convention misread, resulting in wrong physical input being driven Fix: Add 100 nF decoupling capacitors at VCC. Verify each input signal with a multimeter or logic probe to confirm which physical pin is at logic low (active). Cross-check the physical pin assignment against the 74HC148 datasheet pinout diagram, not a generic encoder diagram.

Frequently asked questions

What is the difference between a basic encoder and a priority encoder?

A basic encoder assumes only one input is active at a time and produces undefined or incorrect output if multiple inputs are simultaneously asserted. A priority encoder handles simultaneous inputs by outputting the binary code of the highest-priority (typically highest-indexed) active input, while ignoring all lower-priority active inputs. It also provides a valid output signal confirming that at least one input is active.

What is the 74HC148 priority encoder and what are its key specifications?

The 74HC148 is an 8-to-3 priority encoder IC in the CMOS 74HC logic family. It has eight active-low inputs (I0–I7, with I7 highest priority), three active-low binary outputs (A0–A2), an active-low enable input (EI), an active-low enable output (EO, active when EI is asserted and no inputs are active), and an active-low group select output (GS, active when any input is asserted while enabled). Supply voltage for 74HC is 2–6 V.

How do I expand an 8-to-3 priority encoder to 16-to-4?

Two 74HC148 ICs can be cascaded. The higher-priority (upper) encoder's EO (enable output) connects to the lower-priority encoder's EI (enable input) — the lower encoder is only enabled if no inputs on the upper encoder are active. The output codes are combined with an additional logic gate to include the fourth output bit, and the GS signals are OR'd to generate the combined valid output.

What logic gates implement a 4-to-2 encoder?

A 4-to-2 encoder requires only two OR gates: one for each output bit. Output A1 = I2 OR I3 (implemented with one two-input OR gate). Output A0 = I1 OR I3 (implemented with one two-input OR gate). A priority version requires additional logic to mask lower-priority inputs when a higher-priority input is active, typically using AND gates and inverters.

What is the Group Select (GS) output on a priority encoder used for?

GS goes active when the encoder is enabled and at least one input is asserted. It is used downstream to determine whether the encoder's binary output is valid — without GS, a three-bit output of 000 is ambiguous: it could mean input I0 is asserted, or it could mean no inputs are asserted (all outputs default to 000 in the active-low convention for the 74HC148). GS distinguishes these two conditions.

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