JK Flip Flop Circuit Diagram: Operation, Truth Table and ICs
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The JK flip-flop is an improvement over the SR flip-flop that eliminates the forbidden state by toggling the output when both inputs are HIGH. It is named after Jack Kilby, the inventor of the integrated circuit, and its circuit diagram shows an SR latch core augmented with feedback from the Q and Q̄ outputs back to the input AND gates. The JK flip-flop is one of the most versatile sequential building blocks, capable of implementing Set, Reset, Hold, and Toggle operations from a single clocked device.
The JK flip-flop has three inputs: J (analogous to Set), K (analogous to Reset), and CLK (clock), plus complementary outputs Q and Q̄. The characteristic equation is Q(t+1) = J·Q̄(t) + K'·Q(t), which can be read as: the next state is 1 if J is HIGH and the current state is 0, or if K is LOW and the current state is 1.
The four operating modes are: 1. HOLD (J=0, K=0): Q(t+1) = Q(t). No change. 2. RESET (J=0, K=1): Q(t+1) = 0. Forces output LOW. 3. SET (J=1, K=0): Q(t+1) = 1. Forces output HIGH. 4. TOGGLE (J=1, K=1): Q(t+1) = Q̄(t). Output inverts on every clock edge.
The toggle mode is the key advantage over the SR flip-flop. Where S=R=1 produces an illegal state in the SR latch, J=K=1 in the JK flip-flop causes controlled toggling.
Gate-level construction: Start with an SR NAND latch at the core. Add two 3-input AND gates at the inputs: AND gate 1 feeds S̅ and receives J, CLK, and Q̄ (feedback from output); AND gate 2 feeds R̅ and receives K, CLK, and Q (feedback from output). The feedback connections are what prevent the forbidden state — when Q=1, the J input path is enabled but the K path to RESET is blocked by Q̄=0, and vice versa.
Race-around condition: In a level-triggered JK flip-flop with a HIGH clock pulse, when J=K=1, the output toggles. If the clock remains HIGH longer than the propagation delay of the latch, the output will toggle multiple times — this is the race-around (racing) condition. It is resolved by using an edge-triggered flip-flop (master-slave configuration) where the output only changes on the rising or falling clock edge, not during the entire HIGH period.
Master-slave JK flip-flop: Consists of two SR latches cascaded. The master latch captures input on the rising clock edge while the slave is isolated; on the falling edge, the master is isolated and the slave updates Q. This ensures the output changes exactly once per clock cycle regardless of J and K values.
Edge-triggered JK flip-flop: The 74HC112 is a dual negative-edge-triggered JK flip-flop with active-LOW preset (PR̅) and clear (CLR̅) asynchronous inputs. It responds to J and K only on the falling edge of CLK. The older 7476 is a dual master-slave positive-pulse-triggered JK flip-flop. The 74HC109 is a dual positive-edge-triggered JK flip-flop.
Applications: JK flip-flops are used in frequency dividers (toggle mode with J=K=1 divides clock frequency by 2), binary counters, shift registers, and finite state machine implementations. Simulate the full JK flip-flop with toggle and hold modes in the free online editor at circuitdiagrammaker.com.
How to wire jk flip flop circuit diagram
- Build the NAND SR core Place two cross-coupled 2-input NAND gates to form the SR latch that stores the state.
- Add the J-K input AND gates Place two 3-input AND gates: AND1 inputs = J, CLK, Q̄; AND2 inputs = K, CLK, Q. Connect AND1 output to S̅ of the latch and AND2 output to R̅.
- Wire the feedback paths Connect Q back to AND2 and Q̄ back to AND1 to implement the feedback that prevents the forbidden state.
- Apply clock signal Connect a square wave or push-button clock to CLK. For edge-triggered behaviour, use a 74HC112 IC instead of the discrete gate construction.
- Test Hold mode Set J=0, K=0 and apply clock pulses. Verify that Q does not change regardless of clock transitions.
- Test Toggle mode Set J=1, K=1 and apply clock pulses. Verify that Q inverts with each active clock edge, confirming frequency division.
- Verify Set and Reset modes Apply J=1,K=0 (expect Q→1) and J=0,K=1 (expect Q→0) with clock pulses, confirming asynchronous-like behaviour at clock edge.
Specifications
| J=0, K=0 (Clock edge) | Q(t+1) = Q(t) — Hold |
|---|---|
| J=0, K=1 (Clock edge) | Q(t+1) = 0 — Reset |
| J=1, K=0 (Clock edge) | Q(t+1) = 1 — Set |
| J=1, K=1 (Clock edge) | Q(t+1) = Q̄(t) — Toggle |
| Characteristic equation | Q(t+1) = J·Q̄(t) + K'·Q(t) |
| Race-around condition | Occurs in level-triggered JK when CLK=1 and J=K=1 |
| Solution to race-around | Master-slave or edge-triggered design |
| IC (dual, negative-edge) | 74HC112 (with PR̅ and CLR̅) |
| IC (dual, master-slave) | 7476 |
| IC (dual, positive-edge) | 74HC109 |
| Clock edge sensitivity | Falling edge (74HC112), Rising edge (74HC109) |
| Supply voltage (74HC) | 2 V – 6 V |
| Propagation delay (74HC112) | ~14 ns at 5 V |
Safety warnings
- Never leave J, K, CLK, PR̅, or CLR̅ pins floating on a 74HC112 — tie unused control pins to VCC or GND to prevent floating-input latch-up.
- Ensure the clock signal voltage does not exceed the IC supply voltage (VCC) as overvoltage on logic inputs can permanently damage CMOS gate oxides.
Tools needed
- 74HC112 dual negative-edge-triggered JK flip-flop IC (or 7476 for master-slave)
- Clock source: function generator, 555 astable, or debounced push-button
- Breadboard and jumper wires
- 5 V regulated power supply
- 2× LEDs and 2× 330 Ω resistors for Q and Q̄ display
- circuitdiagrammaker.com for schematic simulation
Common mistakes
- Using a level-triggered JK implementation without addressing the race-around condition, causing multiple toggles per clock pulse when J=K=1.
- Forgetting to connect the feedback wires from Q to AND2 and Q̄ to AND1, which reduces the circuit to an ordinary SR latch without the toggle mode.
- Applying asynchronous preset (PR̅) and clear (CLR̅) while the clock is active on a 74HC112, which can cause meta-stability.
- Confusing the active edge of the 74HC112 (falling) with the 74HC109 (rising), resulting in latching on the wrong clock transition.
- Leaving J or K inputs floating on the IC, which can cause undefined behaviour due to internal TTL input currents.
Troubleshooting
- Output toggles multiple times per clock pulse
- Cause: Level-triggered implementation with J=K=1 and a long clock HIGH period — race-around condition. Fix: Replace with an edge-triggered IC such as 74HC112, or ensure the clock pulse width is shorter than the propagation delay of the latch.
- Toggle mode (J=K=1) does not change Q
- Cause: Feedback wires from Q and Q̄ are missing or disconnected, disabling the AND gates that enable the toggle path. Fix: Verify that Q is connected to one AND gate input and Q̄ to the other AND gate input.
- Asynchronous clear does not work on 74HC112
- Cause: CLR̅ pin is left floating HIGH and not driven LOW. Fix: Drive CLR̅ actively LOW to clear Q, or tie it to VCC if asynchronous clear is not needed.
Frequently asked questions
What is a JK flip flop circuit diagram?
It shows a clocked SR latch core with two AND gates that include feedback from Q and Q̄ back to the J and K input paths, enabling four distinct operating modes including toggle.
What is the truth table for a JK flip flop?
J=0,K=0→Hold; J=0,K=1→Q=0(Reset); J=1,K=0→Q=1(Set); J=1,K=1→Toggle (Q inverts). All state changes occur on the active clock edge.
What is the characteristic equation of a JK flip flop?
Q(t+1) = J·Q̄(t) + K'·Q(t), meaning the next state is SET if J is active and the flip-flop is currently RESET, or HELD if K is inactive and the flip-flop is currently SET.
What IC number is the JK flip flop?
The 74HC112 is the standard dual negative-edge-triggered JK flip-flop. The 7476 is an older dual master-slave JK device.
What is the race-around condition in a JK flip flop?
When a level-triggered JK flip-flop has J=K=1 and the clock is HIGH, the output toggles multiple times within the same clock pulse, causing unpredictable final state. Edge-triggering solves this.
How does a JK flip flop differ from an SR flip flop?
The JK flip-flop adds Q and Q̄ feedback to the input AND gates, replacing the SR's forbidden state (S=R=1) with a useful toggle operation (J=K=1).
How is a JK flip flop used as a frequency divider?
Connecting J=K=1 makes the flip-flop toggle on every active clock edge, dividing the clock frequency by exactly 2. Cascading n flip-flops in this configuration divides by 2ⁿ.