SR Flip Flop Circuit Diagram: NAND and NOR Latch Explained
This is a free printable sr flip flop circuit diagram: download the diagram as SVG or open it and print to paper or PDF.
An SR flip-flop (Set-Reset flip-flop) is the most fundamental bistable memory element, capable of storing one bit by latching into either a SET state (Q=1) or a RESET state (Q=0). It is constructed from two cross-coupled NAND gates or two cross-coupled NOR gates, and it forms the foundation for all more complex flip-flop types including JK, D, and T flip-flops. Understanding the SR flip-flop circuit diagram is the essential first step toward digital sequential circuit design.
The SR flip-flop has two inputs, S (Set) and R (Reset), and two complementary outputs, Q and Q̄. In normal operation Q and Q̄ are always logical complements of each other. The key characteristic is memory: when both inputs return to the inactive state the flip-flop retains (latches) its last state.
NOR-gate SR latch: Constructed from two 2-input NOR gates with cross-coupled feedback. Gate 1 computes Q = NOR(R, Q̄) and Gate 2 computes Q̄ = NOR(S, Q). Active-HIGH inputs: S=1, R=0 → Q=1 (SET); S=0, R=1 → Q=0 (RESET); S=0, R=0 → Q unchanged (HOLD); S=1, R=1 → forbidden (both outputs forced to 0, violating the complementary requirement and producing unpredictable results when inputs are removed simultaneously).
NAND-gate SR latch: Constructed from two cross-coupled NAND gates. This version uses active-LOW inputs (S̅ and R̅). Gate 1: Q = NAND(S̅, Q̄); Gate 2: Q̄ = NAND(R̅, Q). S̅=0, R̅=1 → Q=1 (SET); S̅=1, R̅=0 → Q=0 (RESET); S̅=1, R̅=1 → HOLD; S̅=0, R̅=0 → forbidden (both Q and Q̄ forced to 1). The NAND latch is more commonly used in ICs because NAND gates are faster and consume less silicon area than NOR gates in standard CMOS processes.
Clocked SR flip-flop: Adds a clock input (CLK) and two AND gates between the S/R inputs and the NAND latch core. The flip-flop accepts new input only when CLK=1 (level-triggered). This prevents unintended state changes from input glitches occurring when the clock is LOW.
Characteristic equation of SR flip-flop: Q(t+1) = S + R'·Q(t), valid only when S·R = 0 (the forbidden condition is excluded). This equation states: the next state equals 1 if S is asserted, 0 if R is asserted, or the current state Q(t) if neither input is active.
IC implementation: A quad 2-input NAND gate IC (74HC00 or 7400) contains four NAND gates — exactly two are needed for one SR latch, so a single 7400 can implement two independent SR latches. Similarly, a 7402 quad NOR gate IC can implement two NOR-based SR latches. The 74HC279 is a dedicated quad SR latch IC.
Hazards and the forbidden state: The S=R=1 (NOR latch) or S̅=R̅=0 (NAND latch) condition is forbidden primarily because it creates an indeterminate next state. If both inputs transition to the inactive level simultaneously, the circuit may oscillate or settle unpredictably into either state. In practice this is avoided by design — JK flip-flops solve this by toggling rather than entering an undefined state when both inputs are 1.
The SR latch appears throughout electronics beyond pure digital logic: debouncing mechanical switches, holding alarm states, and inside RAM cells. Build and simulate an SR latch with just four NAND gate symbols in the free online editor at circuitdiagrammaker.com.
How to wire sr flip flop circuit diagram
- Choose gate type Decide between a NAND-based latch (active-LOW inputs) or a NOR-based latch (active-HIGH inputs) based on your logic-level convention.
- Place two cross-coupled gates In the schematic editor, place two NAND (or NOR) gates. Connect the output of Gate 1 to one input of Gate 2, and the output of Gate 2 to one input of Gate 1.
- Label the inputs and outputs Connect the free input of Gate 1 to S̅ (or S for NOR) and the free input of Gate 2 to R̅ (or R). Label the Gate 1 output Q and Gate 2 output Q̄.
- Add pull-up resistors for NAND latch For active-LOW inputs, attach 10 kΩ pull-up resistors from each input to VCC so the latch holds state when no active signal is applied.
- Test SET operation Drive S̅ LOW (NAND) or S HIGH (NOR) while keeping R inactive. Confirm Q goes HIGH and Q̄ goes LOW.
- Test RESET operation Drive R̅ LOW (NAND) or R HIGH (NOR) while keeping S inactive. Confirm Q goes LOW and Q̄ goes HIGH, then remove the input and confirm the latch holds.
- Verify memory (hold state) Set both inputs to their inactive levels and confirm Q retains its last value through power-cycling the logic states on surrounding inputs.
Specifications
| S=0, R=0 (NOR latch) | Q = Q (Hold — no change) |
|---|---|
| S=1, R=0 (NOR latch) | Q = 1 (SET) |
| S=0, R=1 (NOR latch) | Q = 0 (RESET) |
| S=1, R=1 (NOR latch) | Q = forbidden (invalid state) |
| S̅=1, R̅=1 (NAND latch) | Q = Q (Hold) |
| S̅=0, R̅=1 (NAND latch) | Q = 1 (SET) |
| S̅=1, R̅=0 (NAND latch) | Q = 0 (RESET) |
| S̅=0, R̅=0 (NAND latch) | Q = forbidden (both outputs →1) |
| Characteristic equation | Q(t+1) = S + R'·Q(t), S·R=0 |
| NAND latch IC | 7400 (quad 2-input NAND) or 74HC279 |
| NOR latch IC | 7402 (quad 2-input NOR) |
| Dedicated SR latch IC | 74HC279 quad SR latch |
| Supply voltage (74HC) | 2 V – 6 V |
Safety warnings
- Do not leave any gate input pin unconnected on a TTL IC; floating inputs can cause excessive current draw and device heating — tie unused inputs to a defined logic level.
- Avoid drawing more than 25 mA per output pin from 74HC devices; always use current-limiting resistors on LEDs connected to IC outputs.
Tools needed
- 7400 quad NAND IC or 7402 quad NOR IC (or 74HC279 dedicated SR latch)
- Breadboard and jumper wires
- 5 V regulated power supply
- 2× LEDs and 2× 330 Ω resistors for Q and Q̄ outputs
- Logic probe or multimeter
- circuitdiagrammaker.com for schematic simulation
Common mistakes
- Using active-HIGH S/R inputs directly on a NAND latch that expects active-LOW inputs, causing the flip-flop to always be in SET or RESET rather than HOLD.
- Floating one input of the cross-coupled gate pair, which causes the output to be indeterminate rather than latching.
- Asserting S=1 and R=1 simultaneously in a NOR latch without awareness that this is the forbidden condition.
- Neglecting to add a clock gate when the SR latch needs to be level-triggered, allowing input glitches to corrupt stored data.
- Confusing the 74HC279 active-LOW pin names with active-HIGH conventions when reading the datasheet.
Troubleshooting
- Q and Q̄ are both the same logic level
- Cause: Both inputs are in the forbidden state (S=R=1 for NOR or S̅=R̅=0 for NAND). Fix: Remove the forbidden input combination and allow the latch to settle; redesign input logic to prevent simultaneous assertion.
- Latch does not hold state and randomly toggles
- Cause: Floating input on one of the cross-coupled gates due to a missing connection or lifted breadboard leg. Fix: Verify continuity on all four gate input/output connections; add a pull-up or pull-down resistor to the affected input.
- Setting S has no effect
- Cause: S signal is not reaching the gate input, or the power supply to the IC is absent. Fix: Probe the S pin directly with a logic probe; check VCC and GND pins of the IC for correct voltage.
Frequently asked questions
What is an SR flip flop circuit diagram?
It shows two cross-coupled logic gates (NAND or NOR) with Set and Reset inputs and complementary Q/Q̄ outputs, forming the simplest one-bit memory circuit.
What is the truth table of an SR flip flop?
For the NOR-based latch: S=0,R=0→Hold; S=1,R=0→Q=1(SET); S=0,R=1→Q=0(RESET); S=1,R=1→Forbidden.
Why is S=R=1 forbidden in an SR flip flop?
It forces both Q and Q̄ to the same logic level (0 for NOR, 1 for NAND), violating the complementary output rule, and causes an indeterminate state when both inputs are removed simultaneously.
What IC is used to build an SR latch?
A single 7400 quad NAND IC provides two independent NAND-based SR latches; alternatively, the dedicated 74HC279 quad SR latch IC is used in production designs.
How does an SR flip flop differ from a JK flip flop?
The JK flip-flop eliminates the forbidden state by toggling Q when both J and K are 1, making it universally applicable without the input restriction required by the SR flip-flop.
What does the hold state mean in an SR flip flop?
When both S and R are inactive (0,0 for NOR or 1,1 for NAND), the flip-flop retains its previous output state indefinitely, which is the memory or latch function.
Can I use an SR flip flop to debounce a switch?
Yes. Connecting a mechanical switch between the S and R inputs of a NAND SR latch (with pull-ups) captures the first bounce as the definitive state, ignoring subsequent contact bounces.