Ladder Diagram for Traffic Light Control: 3 PLC Methods with Full Rung-by-Rung Solutions
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A PLC ladder diagram for traffic light control sequences Green, Yellow, and Red outputs using timers so that only one light is on at a time and each phase holds for the correct duration. This guide presents three methods — chained TON timers, TP pulse timers, and a state-machine approach — along with a 4-way intersection extension, pedestrian crossing integration, and emergency preemption, so you have a complete reference from beginner to production-level design.
Traffic light control is one of the most widely taught PLC ladder logic examples because it combines three fundamental concepts in a single program: sequential output control, timer-based state transitions, and mutual exclusion (only one light energised at a time). Getting those three things right in ladder logic is the foundation for conveyor sequences, batch processes, and dozens of other industrial automation patterns.
Before writing a single rung, define the I/O allocation. For a basic single-direction traffic light the inputs are a master Start/Stop bit (I0.0) and an optional manual override (I0.1). The outputs are Green (Q0.0), Yellow (Q0.1), and Red (Q0.2). Write this table down — it prevents address confusion when you have multiple timers whose done bits look similar.
Method 1 — Chained TON Timers (simplest, best for learning):
This is the go-to approach for students and for small single-direction applications. It chains three TON (on-delay) timers so the done bit of each timer starts the next phase. A typical timing diagram uses Green for 30 seconds, Yellow for 5 seconds, and Red for 35 seconds (70-second cycle total — industry-typical for a single-approach light). The key design decision is how to reset the sequence. The cleanest approach is to use the done bit of the final Red timer to reset all timer accumulated values and restart from Green.
Rung 1 — Start Green: XIC Start_PB (I0.0) AND XIO T_Red.DN (timer done bit) drives OTE Green (Q0.0). In words: Green is ON while the system is started AND the red-phase timer has not yet completed. On first power-up with all timer DNs FALSE, this rung energises Green immediately.
Rung 2 — Green TON timer (T_Green, PRE=30s): XIC Start_PB AND XIC Green (Q0.0) enables TON T_Green. The timer begins counting as soon as Green energises. When ACC reaches 30 s, T_Green.DN goes TRUE.
Rung 3 — Start Yellow: XIC Start_PB AND XIC T_Green.DN AND XIO T_Yellow.DN drives OTE Yellow (Q0.1). Yellow energises only when the Green timer has finished and the Yellow timer has not yet finished.
Rung 4 — Yellow TON timer (T_Yellow, PRE=5s): XIC Start_PB AND XIC Yellow (Q0.1) enables TON T_Yellow.
Rung 5 — Start Red: XIC Start_PB AND XIC T_Yellow.DN AND XIO T_Red.DN drives OTE Red (Q0.2).
Rung 6 — Red TON timer (T_Red, PRE=35s): XIC Start_PB AND XIC Red (Q0.2) enables TON T_Red.
Rung 7 — Reset cycle: XIC T_Red.DN drives RES T_Green, RES T_Yellow, RES T_Red on three sub-rungs. When Red completes, all timers reset and the sequence restarts from Rung 1.
At no point can two outputs be simultaneously TRUE in this design: the Green rung is gated by XIO T_Red.DN, Yellow is gated by XIC T_Green.DN AND XIO T_Yellow.DN, and Red is gated by XIC T_Yellow.DN. Trace through the logic at any point in the cycle and only one output will be energised.
Method 2 — TP Pulse Timers: The TP (pulse timer) instruction outputs a fixed-width TRUE pulse each time its enable input has a rising edge. By chaining the Q output of one TP as the enable rising-edge trigger for the next, you build a fixed-period sequence. This approach is common on Siemens S7 platforms where TP is a native instruction. The advantage is that each phase duration is explicitly set in one place (the PT parameter) with no reset rung required — the timer resets automatically when Q goes FALSE.
Method 3 — State Machine (scalable, production-grade): For a 4-way intersection (North/South and East/West) or any sequence with more than three states, the state-machine approach is far more maintainable. Assign an internal memory bit to each state: M0.0=Green_NS, M0.1=Yellow_NS, M0.2=Red_NS, M0.3=AllRed, M0.4=Green_EW, M0.5=Yellow_EW, M0.6=Red_EW. Only one state bit is TRUE at any time — an exclusive-state rung using XIO contacts for all other state bits enforces this.
The all-red clearance state (M0.3) is a short 2-second state inserted between one direction going red and the other going green. It ensures both directions see red simultaneously before the new green phase starts, clearing any vehicles that ran a late yellow. This is a safety-critical requirement in real traffic engineering and is often the missing piece in student examples.
Pedestrian crossing integration adds an input (I0.2, XING button). A memory bit (M1.0, XING_requested) latches when pressed. At the end of the current state the state machine checks M1.0 and inserts a pedestrian green phase before the all-red clearance.
Emergency preemption (I0.3, EMRG) immediately interrupts the normal sequence by OTU-ing all state bits, forcing a 15-second all-red hold on all outputs, then restarting the sequence. This is implemented with a high-priority rung at the top of the program that runs before the state-machine rungs.
Verification checklist: force Start TRUE and confirm Green energises. Wait 30 s and confirm Green de-energises and Yellow energises. Wait 5 s and confirm Yellow de-energises and Red energises. At no point during any transition should two colour outputs be simultaneously TRUE (monitor Q0.0, Q0.1, Q0.2 in the simulator's online view). Confirm the cycle repeats automatically.
Open circuitdiagrammaker's free ladder diagram tool to build and simulate your traffic light program — drag and drop contacts, set timer presets, force inputs, and watch the rung states update in real time before you write a line of code to a physical PLC.
How to wire ladder diagram for traffic light control
- Define I/O allocation Input I0.0 = Start/Stop master bit. Output Q0.0 = Green lamp, Q0.1 = Yellow lamp, Q0.2 = Red lamp. For a 4-way extension: Q1.0 = Green_EW, Q1.1 = Yellow_EW, Q1.2 = Red_EW. Write this table before building any rung.
- Rung 1 — Energise Green (first phase) XIC Start (I0.0) in series with XIO T_Red.DN. Output: OTE Green (Q0.0). This rung energises Green on start-up and holds it until the Red timer completes a full cycle, at which point the reset rung clears T_Red.DN and this rung re-energises Green for the next cycle.
- Rung 2 — TON Green timer (T_Green, PRE = 30 s) XIC Start (I0.0) AND XIC Green (Q0.0) enables TON T_Green with preset 30 000 ms (or 30 in units of seconds, platform-dependent). When ACC = PRE, T_Green.DN goes TRUE and enables the Yellow rung.
- Rung 3 — Energise Yellow (second phase) XIC Start (I0.0) AND XIC T_Green.DN AND XIO T_Yellow.DN. Output: OTE Yellow (Q0.1). Yellow is only possible after Green's timer has completed and before Yellow's own timer completes.
- Rung 4 — TON Yellow timer (T_Yellow, PRE = 5 s) XIC Start (I0.0) AND XIC Yellow (Q0.1) enables TON T_Yellow with preset 5 000 ms. When ACC = PRE, T_Yellow.DN goes TRUE and enables the Red rung.
- Rung 5 — Energise Red (third phase) XIC Start (I0.0) AND XIC T_Yellow.DN AND XIO T_Red.DN. Output: OTE Red (Q0.2). Red holds until its own timer (T_Red, PRE = 35 s) completes, at which point the reset rung fires.
- Rung 6 — TON Red timer (T_Red, PRE = 35 s) XIC Start (I0.0) AND XIC Red (Q0.2) enables TON T_Red with preset 35 000 ms. When complete, T_Red.DN triggers the reset rung.
- Rung 7 — Reset all timers to restart cycle XIC T_Red.DN drives three consecutive RES instructions: RES T_Green, RES T_Yellow, RES T_Red. Resetting T_Red.DN allows Rung 1 to re-energise Green and the 70-second cycle begins again automatically.
- Rung 8 — All-red clearance (4-way extension) Insert a 2-second all-red state between any direction transition. Use a state bit (M0.3) that forces all six lamp outputs OFF except Red for all directions. A TON timer (T_AllRed, PRE = 2 s) advances to the next phase. This prevents simultaneous green on crossing approaches.
Specifications
| Cycle time (typical single-direction) | Green 30 s + Yellow 5 s + Red 35 s = 70 s |
|---|---|
| All-red clearance interval | 2–4 s (insert between opposing-direction transitions) |
| Minimum I/O — single direction | 1 input (Start), 3 outputs (G/Y/R) |
| Minimum I/O — 4-way intersection | 1–2 inputs (Start, XING), 6 outputs (G/Y/R × 2 directions) |
| Timer instructions used | TON (method 1), TP (method 2) |
| Minimum rungs — chained TON | 7 rungs |
| Minimum rungs — 4-way state machine | 15–20 rungs |
| PLC platforms compatible | IEC 61131-3 compliant: Siemens S7, Allen-Bradley MicroLogix/CompactLogix, Omron CP/CJ, Schneider Modicon |
Safety warnings
- Never deploy a traffic light PLC program to public road infrastructure without full compliance with national traffic signal standards (e.g. ITE MUTCD in the USA, Traffic Signs Manual in the UK). This guide is for educational and private-site use only.
- The all-red clearance state is a safety requirement, not an optional feature. Omitting it creates a condition where vehicles from opposing directions can simultaneously have a green signal during a transition.
- Emergency preemption inputs connected to emergency vehicle detection systems must be treated as safety-critical circuits and wired with appropriate redundancy and monitoring per IEC 62061.
- Any traffic control system installed on a public road must undergo independent safety validation by a qualified traffic engineer and comply with local regulatory approval processes.
Tools needed
- circuitdiagrammaker.com ladder diagram editor or any IEC 61131-3 ladder tool (TIA Portal, Studio 5000, OpenPLC, CX-Programmer)
- I/O allocation spreadsheet listing all input and output PLC addresses with descriptions
- Timing diagram showing phase durations for each direction and the all-red interval
- State table (for state-machine method): list of states, state bits, timer bits, and active outputs per state
- Test script: ordered list of input force conditions and expected output states for verification
Common mistakes
- Omitting the all-red clearance state in a 4-way design — all competitors' examples do this; it is a safety deficiency in any real installation
- Using OTE (non-retentive) output coils for lamp outputs without exclusive-state logic — if two rungs can energise the same lamp at different points in the cycle, the last rung evaluated wins each scan, causing flicker or stuck states
- Forgetting to add the reset rung for chained TON timers — without it the Red timer's done bit stays TRUE permanently after the first cycle and Green can never re-energise
- Setting all timer presets to the same value for simplicity during development, then forgetting to adjust to correct phase durations before deployment
- Not accounting for PLC scan time in very short phases — a Yellow phase shorter than 3 scan cycles may be missed entirely on older slow PLCs; always use TP or one-shot logic for sub-second transitions
Troubleshooting
- Traffic light cycles correctly once then gets stuck on Red permanently
- Cause: The reset rung is missing or the RES instruction is targeting the wrong timer tag, so T_Red.DN never clears and Rung 1 (Green) never re-energises Fix: Verify the reset rung has XIC T_Red.DN gating a RES instruction on all three timer tags (T_Green, T_Yellow, T_Red). In run mode, force T_Red.DN TRUE and watch all three timer ACC values drop to zero.
- Green and Yellow are both ON simultaneously
- Cause: The XIO T_Yellow.DN gate is missing from the Yellow output rung, allowing Yellow to energise while T_Green.DN is still TRUE during the scan before T_Yellow's rung runs Fix: Add XIO T_Yellow.DN in series on the Yellow output rung. Review all output rungs to ensure each has exclusive gating conditions that prevent simultaneous energisation.
- The sequence skips Yellow and jumps directly from Green to Red
- Cause: T_Yellow preset is set to zero or the Yellow rung has an inverted XIO condition that immediately de-energises it on the same scan it energised Fix: Check T_Yellow.PRE is a non-zero positive value. In single-step mode, manually step through the scan after T_Green.DN goes TRUE and confirm Yellow energises for at least one scan.
- Emergency preemption input (I0.3) causes a momentary Green flicker before going to all-red
- Cause: The emergency rung is positioned below the normal-state output rungs, so the state outputs update before the emergency rung can clear them in the same scan Fix: Move all emergency preemption rungs to the top of the program (lowest rung number) so they execute first in every scan cycle.
- Pedestrian crossing button latches but XING phase never activates
- Cause: The XING_request memory bit (M1.0) is being reset by the sequence reset rung as well as the XING phase completion rung, so it clears before the state machine reaches the XING-check transition Fix: Use a dedicated XING reset rung that only fires when the XING phase output is active (XIC XING_phase AND XIC T_XING.DN drives RES M1.0). Do not include M1.0 in the general cycle reset rung.
Frequently asked questions
How does a PLC control a traffic light?
The PLC executes ladder rungs that energise one lamp output at a time and use TON or TP timer instructions to hold each phase for a defined duration. When a timer's done bit goes TRUE it de-energises the current lamp and energises the next one. The cycle repeats continuously as long as the master Start bit is TRUE.
How many rungs does a basic traffic light PLC program need?
A single-direction chained-TON traffic light needs a minimum of 7 rungs: one per lamp output (3), one per timer (3), and one reset rung. A 4-way intersection state machine typically uses 15–20 rungs depending on the number of states and optional pedestrian/preemption rungs.
What is the difference between TON and TP timer in a traffic light program?
TON (on-delay) starts timing when its enable rung is TRUE and latches the done bit TRUE when ACC reaches PRE. TP (pulse timer) outputs a fixed-width pulse each time it detects a rising edge on its enable input and automatically resets. For a chained sequence TON requires an explicit reset rung; TP is self-resetting but requires edge-detection logic to chain states.
What is an all-red clearance interval and why is it needed?
An all-red clearance interval is a brief period — typically 2 to 4 seconds — during which all approaches to an intersection show Red simultaneously. It provides a safety buffer to clear any vehicle that entered on a late Yellow or ran the just-expired Green, before the crossing direction receives its Green signal. Without it, a slow vehicle from one direction could still be in the intersection when the opposing direction starts moving.
What timers are used in a traffic light ladder diagram?
TON (on-delay timer) is the most common choice because its done bit latches TRUE until explicitly reset, making rung sequencing straightforward. TP (pulse timer) is an alternative for fixed-width outputs. TOF (off-delay) is rarely used in traffic light sequences.
What PLC software can I use to simulate a traffic light program for free?
circuitdiagrammaker's free online ladder diagram tool, OpenPLC Runtime (free, open-source, installs on Windows/Linux/Raspberry Pi), and the PLCSIM trial included with Siemens TIA Portal all support traffic light simulation. The circuitdiagrammaker browser tool requires no installation.
How do I add a pedestrian crossing to a PLC traffic light program?
Add an input bit for the pedestrian pushbutton (I0.2). Use a latch rung to set a XING_request memory bit (M1.0) when pressed. At the transition from Red back to Green, check M1.0: if TRUE, insert a pedestrian Green phase (all vehicle outputs Red, pedestrian Walk output Q0.3 ON) for 20–30 s, then clear M1.0 and continue the normal sequence.
Why must only one lamp be ON at a time, and how do ladder interlocks enforce this?
Two lamps being simultaneously active (e.g. Green and Red) would be a dangerous conflicting signal. In the chained-TON method this is enforced logically by the timer gate conditions: Yellow can only energise after T_Green.DN and before T_Yellow.DN, making simultaneous Green+Yellow structurally impossible. In a state-machine approach, XIO contacts for all other state bits on each state's output rung enforce exclusivity at the rung level.