Ladder Diagram for Logic Gates: AND, OR, NOT, NAND, NOR, and XOR in PLC Ladder Logic

This is a free printable ladder diagram for logic gates: download the diagram as SVG or open it and print to paper or PDF.

Every Boolean logic gate has a direct equivalent in PLC ladder logic — AND is two contacts in series, OR is two branches in parallel, NOT is a normally closed (XIO) contact, and the compound gates NAND, NOR, and XOR all follow from combining those primitives. Understanding these one-to-one mappings lets you translate digital logic circuits into working PLC programs and reason about ladder rungs using familiar Boolean algebra.

Ladder logic was designed by early PLC engineers who were replacing relay panels, not computer circuits. Despite that origin, it implements every Boolean logic function that a gate-level circuit diagram can express. The IEC 61131-3 standard formalises this with the Ladder Diagram (LD) language, which defines exactly how contacts and coils evaluate to Boolean TRUE or FALSE on each PLC scan.

The fundamental mapping rule is: contacts in series implement AND logic (all must be TRUE for current to flow), contacts in parallel implement OR logic (any branch being TRUE allows current to flow), and a normally closed (XIO) contact implements NOT logic (it evaluates TRUE when its referenced bit is FALSE and vice versa).

AND Gate in Ladder Logic:

A 2-input AND gate output is TRUE only when both input A AND input B are TRUE. In ladder logic this is implemented by placing two XIC (normally open) contacts in series on a single rung:

|--[XIC A]--[XIC B]--( OTE Y )--|

Truth table: A=0, B=0 → Y=0. A=0, B=1 → Y=0. A=1, B=0 → Y=0. A=1, B=1 → Y=1.

Industrial example: a machine guard is open (I0.0) AND a start button is pressed (I0.1) → enable the tool motor (Q0.0). Both conditions must be simultaneously TRUE to energise the output.

Extending to 3 or more inputs is simply adding more XIC contacts in series. An N-input AND gate requires N XIC contacts in series.

OR Gate in Ladder Logic:

A 2-input OR gate output is TRUE when input A OR input B (or both) are TRUE. In ladder logic this is two parallel branches on the same rung, each leading to the same output coil:

|--[XIC A]--+--( OTE Y )--| | | +--[XIC B]--+

Truth table: A=0, B=0 → Y=0. A=0, B=1 → Y=1. A=1, B=0 → Y=1. A=1, B=1 → Y=1.

Industrial example: either a high-level float switch (I0.0) OR a high-pressure sensor (I0.1) triggers a drain valve output (Q0.1). Either alarm condition independently activates the output.

NOT Gate in Ladder Logic:

A NOT gate output is TRUE when the input is FALSE and vice versa. In ladder logic this is a single XIO (normally closed) contact:

|--[XIO A]--( OTE Y )--|

Truth table: A=0 → Y=1. A=1 → Y=0.

XIO contacts are ubiquitous in real programs — the stop button on every motor starter is an XIO contact wired to a physically NC pushbutton, providing fail-safe operation: if the wiring breaks, the contact opens and the motor stops (the NC-wired / XIO ladder combination achieves fail-safe at both the hardware and software layers).

NAND Gate in Ladder Logic:

NAND is AND followed by NOT: output is FALSE only when both inputs are TRUE, TRUE in all other cases. There are two equivalent ladder implementations:

Method 1 — Series XIO contacts: place two XIO contacts in series. This works because by De Morgan's theorem, NOT(A AND B) = (NOT A) OR (NOT B), but since the XIO contacts individually negate their respective bits, two XIO contacts in series evaluate the De Morgan equivalent correctly.

|--[XIO A]--[XIO B]--( OTE Y )--|

Method 2 — AND rung with inverted output: use a dedicated memory bit for the AND result, then invert it on a second rung with XIO.

Truth table: A=0, B=0 → Y=1. A=0, B=1 → Y=1. A=1, B=0 → Y=1. A=1, B=1 → Y=0.

Note on Method 1 correctness: XIO A in series with XIO B evaluates to TRUE when A=0 AND B=0 (both FALSE), or A=0 AND B=1 (one FALSE), or A=1 AND B=0 (other FALSE), but FALSE when A=1 AND B=1. This matches the NAND truth table. The reason is that the series XIO pattern evaluates (NOT A) AND (NOT B) — which by De Morgan's theorem equals NOT(A OR B), which is NOR, not NAND. To correctly implement NAND in a single rung you must use parallel OR branches with individual XIO contacts.

NAND in a single rung (correct):

|--[XIO A]--+--( OTE Y )--| | | +--[XIO B]--+

This implements: NOT A OR NOT B = NOT(A AND B) = NAND. Verify with the truth table.

NOR Gate in Ladder Logic:

NOR is OR followed by NOT: output is TRUE only when both inputs are FALSE. In ladder logic: series XIO contacts (since series XIO evaluates (NOT A) AND (NOT B) = NOT(A OR B) = NOR):

|--[XIO A]--[XIO B]--( OTE Y )--|

Truth table: A=0, B=0 → Y=1. A=0, B=1 → Y=0. A=1, B=0 → Y=0. A=1, B=1 → Y=0.

Industrial example: a motor is allowed to run only when neither a door-open sensor (I0.0) nor an E-stop (I0.1) is active. Both must be FALSE (safe state) for the permit output (Q0.2) to be TRUE.

XOR Gate in Ladder Logic:

XOR (exclusive OR) output is TRUE when inputs A and B are different — one TRUE and one FALSE — but not when both are the same. XOR requires a combination of contacts because no single contact type implements it directly:

Rung 1 (A=1, B=0 branch): |--[XIC A]--[XIO B]--+--( OTE Y )--| | | Rung 1 continuation (A=0, B=1 branch): +--[XIO A]--[XIC B]--+

In a single rung, both parallel branches feed the same output coil. Branch 1: XIC A AND XIO B (TRUE when A=1 and B=0). Branch 2: XIO A AND XIC B (TRUE when A=0 and B=1). The OR of those two branches is the XOR function.

Truth table: A=0, B=0 → Y=0. A=0, B=1 → Y=1. A=1, B=0 → Y=1. A=1, B=1 → Y=0.

Industrial example: a limit switch (I0.0) should confirm a part is present at exactly one of two sensor positions (I0.0 or I0.1) — not both (jam condition) and not neither (absent). The XOR output drives an alarm bit when the part is in an inconsistent position.

XNOR is the complement of XOR — output TRUE when both inputs match. Implement it with parallel (XIC A AND XIC B) OR (XIO A AND XIO B) branches, or negate the XOR result with an additional memory bit.

Practical notes on multi-gate programs: in real PLC programs it is rare to implement logic gates as isolated rungs. Instead, several gates are combined within a single rung using the series and parallel contact structure to build complex Boolean expressions. You can verify any multi-gate rung by constructing its truth table — enumerate all input combinations, trace each rung branch, and confirm the output matches your intent.

Build and verify your logic gate ladder diagrams in the free circuitdiagrammaker online editor — force each input combination and confirm the output state matches the truth table before writing to a physical PLC.

How to wire ladder diagram for logic gates

1. AND gate — two XIC contacts in series Place XIC contact for input A (I0.0), then XIC contact for input B (I0.1) in series on the same rung, connected to OTE output Y (Q0.0). The rung only completes (Y=TRUE) when both A and B are simultaneously TRUE. Verify with truth table: force A=0 B=0 → Q0.0 off; A=1 B=0 → off; A=0 B=1 → off; A=1 B=1 → Q0.0 on.
2. OR gate — two parallel branches Create two parallel branches on the same rung both feeding OTE Y (Q0.0). Branch 1: XIC A (I0.0). Branch 2: XIC B (I0.1). The rung completes (Y=TRUE) when either A OR B (or both) are TRUE. Verify: A=0 B=0 → off; A=1 B=0 → on; A=0 B=1 → on; A=1 B=1 → on.
3. NOT gate — single XIO (normally closed) contact Place a single XIO contact for input A (I0.0) on the rung, connected to OTE Y (Q0.0). Y is TRUE when A is FALSE and FALSE when A is TRUE. This is how every NC stop button and E-stop is implemented in ladder logic — fail-safe by design.
4. NAND gate — parallel XIO branches Create two parallel branches: Branch 1: XIO A (I0.0). Branch 2: XIO B (I0.1). Both feed OTE Y (Q0.0). This evaluates NOT(A) OR NOT(B) which equals NOT(A AND B) — the NAND function. Verify: A=1 B=1 → off (the only FALSE case); all other combinations → on.
5. NOR gate — two XIO contacts in series Place XIO A (I0.0) in series with XIO B (I0.1), feeding OTE Y (Q0.0). This evaluates NOT(A) AND NOT(B) = NOT(A OR B) — the NOR function. Only when both A and B are FALSE (both XIO contacts are TRUE) does the rung complete. Verify: A=0 B=0 → on; any other combination → off.
6. XOR gate — two cross-branches Create two parallel branches on one rung feeding OTE Y (Q0.0). Branch 1: XIC A (I0.0) in series with XIO B (I0.1). Branch 2: XIO A (I0.0) in series with XIC B (I0.1). Branch 1 is TRUE only when A=1 and B=0. Branch 2 is TRUE only when A=0 and B=1. Together they form XOR. Verify: A=0 B=0 → off; A=1 B=1 → off; A=1 B=0 → on; A=0 B=1 → on.
7. XNOR gate — two matching branches Create two parallel branches: Branch 1: XIC A (I0.0) in series with XIC B (I0.1). Branch 2: XIO A (I0.0) in series with XIO B (I0.1). XNOR is TRUE when both inputs match (both ON or both OFF). This is the complement of XOR. Verify: A=0 B=0 → on; A=1 B=1 → on; A=1 B=0 → off; A=0 B=1 → off.
8. Verify every gate with truth table forcing In your simulator (circuitdiagrammaker or PLC programming software), run the program and systematically force each input combination (all 2^N combinations for N inputs). Confirm every output state matches the gate's truth table. Document the results in your I/O commissioning record.

Specifications

Safety warnings

• Implementing safety logic (E-stop, guard interlock, two-hand control) requires more than correct Boolean gate logic — safety functions must be implemented on safety-rated PLCs (IEC 62061 / ISO 13849) with hardware diversity and periodic proof-testing. A standard PLC with a logically correct NOR gate rung is not a certified safety function.
• Do not use a single XIO contact as the sole stop mechanism for a motor — wire the stop pushbutton as a physically NC contact AND use an XIO contact in the ladder so that a broken wire causes the motor to stop (fail-safe design).
• Duplicate output coils in a ladder program can make gate logic appear to work in simulation but behave unpredictably on a real PLC. Verify that each output address appears in only one OTE coil instruction across the entire program.

Tools needed

• circuitdiagrammaker.com ladder diagram editor or any IEC 61131-3 compliant PLC programming tool (TIA Portal, Studio 5000, OpenPLC, CX-Programmer)
• Truth tables for each gate constructed before building the rung — on paper or in a spreadsheet
• I/O allocation listing input bits (I0.0, I0.1, etc.) and output bits (Q0.0, Q0.1, etc.) for each gate
• Boolean algebra reference (De Morgan's theorem, absorption, distribution laws) for verifying and simplifying complex multi-gate rungs
• Simulator force-table or contact monitoring panel to systematically test all input combinations

Common mistakes

• Confusing NOR and NAND ladder arrangements: series XIO = NOR, parallel XIO = NAND — beginners frequently swap these, which makes the output behave correctly for three of the four input combinations and incorrectly for only A=1 B=1
• Using OTE (non-retentive) output for a gate result that needs to be memorised between scans — if a latch or memory function is needed, use OTL/OTU or a dedicated memory bit with a seal-in rung
• Implementing XOR with only two contacts (e.g. XIC A in series with XIO B) — this only covers half the XOR truth table and gives a wrong result when A=0, B=1
• Applying De Morgan's theorem incorrectly when simplifying a multi-gate rung — always construct the truth table of the simplified expression and compare it row by row with the original
• Forgetting that PLC scan order matters for self-referencing bits — a bit written by an OTE coil in Rung 5 is available to contacts in Rung 6 onward in the same scan, but rungs 1–4 see the previous scan's value

Troubleshooting

NAND rung output stays FALSE when one input is TRUE and the other is FALSE — should be TRUE

Cause: The NAND rung is using series XIO contacts instead of parallel XIO branches. Series XIO implements NOR, not NAND. Fix: Restructure the rung to use two parallel branches, each containing one XIO contact. Verify with the truth table: A=1 B=0 should give Y=TRUE.

XOR output is TRUE when both inputs are TRUE (should be FALSE)

Cause: The XOR rung is using only one parallel branch (e.g. XIC A OR XIC B without the cross-NOT conditions), implementing OR instead of XOR Fix: Implement XOR as two parallel branches: Branch 1 = XIC A in series with XIO B; Branch 2 = XIO A in series with XIC B. Both inputs TRUE will mean both branches are FALSE (T AND F = F for Branch 1; F AND T = F for Branch 2), so the output will correctly be FALSE.

NOR output is TRUE even when one input is TRUE (should be FALSE)

Cause: The rung uses parallel branches (OR) of XIO contacts instead of series XIO — implementing NAND-like logic rather than NOR Fix: Place both XIO contacts in series on a single rung branch. This evaluates NOT(A) AND NOT(B) = NOR. The rung only completes when both inputs are FALSE.

NOT gate output is always FALSE regardless of input

Cause: The contact is configured as XIC (normally open) instead of XIO (normally closed), so it conducts only when the input is TRUE — the opposite of NOT Fix: Change the contact type to XIO. In most PLC software this is a right-click property change or a separate button on the contact toolbar. Confirm the symbol shows a diagonal line through the contact (XIO) rather than no line (XIC).

Complex multi-gate rung produces wrong output for one specific input combination

Cause: A De Morgan transformation was applied incorrectly during simplification, or a series/parallel grouping brackets the wrong contacts together Fix: Construct the complete truth table for all input combinations. Trace each combination through the rung manually, noting which contacts are TRUE or FALSE at each step. Identify the failing combination and compare to the intended Boolean expression.

Frequently asked questions

What is the ladder logic equivalent of an AND gate?

Two XIC (normally open) contacts in series on a rung. Current flows through the rung — and the output coil energises — only when both contacts are simultaneously TRUE, which is exactly AND logic.

What is the ladder logic equivalent of an OR gate?

Two parallel branches on the same rung, each with one XIC contact, both feeding the same output coil. If either branch carries current, the output energises — this is OR logic.

How do you implement a NOT gate in ladder logic?

Use a single XIO (examine if open, or normally closed) contact. An XIO contact evaluates TRUE when the bit it references is FALSE, and FALSE when the bit is TRUE — directly implementing logical NOT.

How do you implement NAND in a ladder diagram?

Use two parallel XIO contacts (one per input) feeding the output coil. This implements NOT(A) OR NOT(B) which, by De Morgan's theorem, equals NOT(A AND B) — the NAND function. Do not use series XIO contacts for NAND; that implements NOR.

How do you implement NOR in a ladder diagram?

Use two XIO contacts in series. This evaluates NOT(A) AND NOT(B) = NOT(A OR B) — the NOR function. The output is TRUE only when both inputs are FALSE.

How do you implement XOR in a ladder diagram?

Use two parallel branches: Branch 1 = XIC A in series with XIO B. Branch 2 = XIO A in series with XIC B. Branch 1 is TRUE only when A=1 and B=0; Branch 2 only when A=0 and B=1. The OR of both branches is XOR.

Is NAND a series or parallel arrangement in ladder logic?

NAND is a parallel arrangement of XIO contacts. Parallel XIO implements NOT(A) OR NOT(B) = NAND. Series XIO implements NOT(A) AND NOT(B) = NOR. The common beginner mistake is confusing the two.

Can you verify logic gate ladder rungs with De Morgan's theorem?

Yes. De Morgan's laws state: NOT(A AND B) = NOT(A) OR NOT(B), and NOT(A OR B) = NOT(A) AND NOT(B). These directly predict the correct contact arrangement for NAND (parallel XIO) and NOR (series XIO). Applying De Morgan's theorem to any complex rung lets you simplify or verify its Boolean expression.

Why does ladder logic use XIC and XIO instead of just gate symbols?

Ladder logic was designed to mimic relay panel drawings that electricians already knew. XIC represents a normally open relay contact (conducts when the relay coil is energised) and XIO represents a normally closed contact (conducts when the relay coil is de-energised). This notation makes the physical panel-to-PLC migration straightforward.

Can you implement a 3-input AND gate in ladder logic?

Yes — simply place three XIC contacts in series on the same rung. For a 3-input OR gate, create three parallel branches each with one XIC contact. Any N-input Boolean gate can be built by extending the series/parallel patterns.

Related diagrams

• ladder diagram examples with solutions
• ladder diagram basics

Free electrical calculators

• Voltage Drop Calculator
• Wire Size Calculator
• Conduit Fill Calculator
• Breaker Size Calculator
• Electrical Load Calculator

Edit this diagram free in the online editor