NOR Gate Circuit Diagram: Boolean Logic, Truth Table & Universal Gate
This is a free printable nor gate circuit diagram: download the diagram as SVG or open it and print to paper or PDF.
A NOR gate outputs HIGH only when ALL of its inputs are LOW — it is the complement of an OR gate. Its Boolean expression is Y = (A + B)'. Like the NAND gate, the NOR gate is universal: every Boolean function can be implemented using NOR gates alone. The standard IC is the 7402, which contains four independent 2-input NOR gates.
The NOR gate combines OR with inversion. For a 2-input NOR gate the Boolean expression is Y = (A + B)'. By De Morgan's theorem this equals Y = A' · B', meaning the output is HIGH only when both inputs are LOW (both complements are HIGH).
Truth table: when A=0, B=0, Y=1 (the only HIGH output row). When A=0, B=1, Y=0; when A=1, B=0, Y=0; when A=1, B=1, Y=0. Compare this to the OR gate: NOR has exactly one HIGH row where OR has three HIGH rows — they are perfect complements.
Logic symbol: the NOR gate looks like an OR gate (curved shield body) but with a bubble at the output tip. This bubble indicates the inversion. In IEC rectangular notation the body has a '≥1' label and an output inversion circle.
Two-transistor NOR circuit: connect two NPN transistors Q1 and Q2 in parallel — both collectors tied together to Vcc through a pull-up resistor R_C (1kΩ), and both emitters tied to GND. Input A drives Q1's base through R_B1 (10kΩ); input B drives Q2's base through R_B2 (10kΩ). The output is taken at the shared collector node. When both inputs are LOW, both transistors are cut off; R_C pulls the output HIGH. When either (or both) inputs go HIGH, that transistor saturates and pulls the collector node to near GND — output LOW. This is a direct positive-logic NOR implementation.
In CMOS technology, a NOR gate is built with two PMOS transistors in series (pull-up network) and two NMOS transistors in parallel (pull-down network). If either NMOS is turned on (either input HIGH), the output is pulled LOW through the parallel NMOS path. Only when both PMOS transistors are on (both inputs LOW) does the series PMOS path pull the output HIGH. This means CMOS NOR pull-up paths are series-connected, making NOR inherently slower than NAND in CMOS — which is why NAND-heavy cell libraries are preferred in modern VLSI.
Integrated circuit: the 7402 is the standard quad 2-input NOR gate IC (TTL, 14-pin DIP). Low-power Schottky: 74LS02. CMOS: 74HC02 and CD4001B. Note that the 7402 pin-out differs from the 7400/7408 arrangement: outputs are on the outer pins. Gate 1 — output on pin 1, inputs on pins 2 and 3; gate 2 — output pin 4, inputs pins 5 and 6; gate 3 — output pin 10, inputs pins 8 and 9; gate 4 — output pin 13, inputs pins 11 and 12. Vcc pin 14, GND pin 7.
Universal gate constructions using NOR (7402): - NOT gate: tie both inputs of a NOR gate together. Y = (A + A)' = A' - OR gate: NOR output inverted by a tied-input NOR. Two NOR gates. - AND gate: invert each input (two NOR-as-NOT gates) then NOR the results: (A' + B')' = A · B by De Morgan. Three NOR gates. - NAND gate: AND construction followed by another NOT. Four NOR gates.
Applications: NOR-based SR latch is the fundamental storage element in sequential logic. Active-LOW enable lines naturally use NOR logic. NOR flash memory arrays use NOR gate topology for fast random-access reads.
Head to the free Circuit Diagram Maker editor to build the NOR-based SR latch — wire two NOR gates in cross-coupled feedback, apply S and R inputs, and observe bistable memory behaviour.
How to wire nor gate circuit diagram
- Gather components Obtain a 7402 quad NOR gate IC, breadboard, 5V supply, two push-buttons, 10kΩ pull-down resistors, a 470Ω resistor, and an LED.
- Note the 7402 pin-out Unlike the 7408/7400, the 7402 outputs are on the outer pins. Gate 1 output is pin 1; inputs are pins 2 and 3. Sketch the pin-out before wiring to avoid miswiring.
- Power the IC Connect pin 14 to +5V and pin 7 to GND. Add a 100nF decoupling capacitor between these power pins.
- Connect inputs Wire push-button switches to pins 2 and 3 with 10kΩ pull-down resistors to GND on each input pin.
- Connect output LED Run pin 1 (output 1Y) through a 470Ω resistor to the LED anode; LED cathode to GND. At power-up (both inputs LOW) the LED should illuminate.
- Test NOR behaviour Press either button (or both): the LED should extinguish immediately. Only when both buttons are released should the LED be on. Confirm all four input combinations match the truth table.
- Build SR latch Use gates 1 and 2: cross-connect output of gate 1 (pin 1) to one input of gate 2 (pin 5), and output of gate 2 (pin 4) back to one input of gate 1 (pin 2). Apply Set and Reset through the remaining inputs to observe bistable memory.
Specifications
| A=0, B=0 | Y=1 |
|---|---|
| A=0, B=1 | Y=0 |
| A=1, B=0 | Y=0 |
| A=1, B=1 | Y=0 |
| Boolean expression | Y = (A + B)' = A' · B' |
| TTL IC (2-input) | 7402 / 74LS02 |
| CMOS IC (2-input) | 74HC02 / CD4001B |
| Supply voltage (TTL) | 5V ±5% |
| Supply voltage (74HC) | 2V – 6V |
| Propagation delay (74LS02) | 10 ns typical |
| Output pin location (7402) | Outer pins (1, 4, 10, 13) — opposite to 7400 |
Safety warnings
- The 7402 output pins are on the opposite positions compared to most other 74xx ICs — always double-check the datasheet before connecting to avoid accidentally driving an IC input with a power-rail short.
- Do not operate the NOR SR latch with both S=1 and R=1 simultaneously in a live system; the metastable output state during transition can cause undefined downstream behaviour in connected circuits.
Tools needed
- 7402 or 74LS02 quad NOR gate IC
- Breadboard and jumper wires
- 5V DC power supply
- Digital multimeter
- LED and 470Ω resistor
- 10kΩ pull-down resistors and 100nF decoupling capacitor
Common mistakes
- Using the 7400 pin-out for the 7402: the two ICs have reversed input/output positions. Wiring gate inputs to 7400 output positions (pins 3, 6, 8, 11) on a 7402 connects to inputs instead, giving wrong results.
- Leaving inputs floating in the NOR-based SR latch: both S and R must be driven to defined logic levels. Floating inputs cause the latch to randomly set or reset due to noise.
- Applying S=1 and R=1 simultaneously to a NOR SR latch: this is the forbidden state, forcing both outputs Q and Q' LOW. Releasing both inputs simultaneously leads to unpredictable final state.
- Forgetting that NOR fan-out is identical to AND/NAND at 10 LS-TTL loads for 74LS02: overloading the output causes voltage drooping below the HIGH threshold.
Troubleshooting
- Output always LOW regardless of input state
- Cause: Input pins 2 and 3 stuck HIGH due to miswiring to Vcc or shorts Fix: Probe each input pin. If either reads HIGH when the switch is open, the pull-down resistor is missing or disconnected.
- SR latch will not hold state (Q resets spontaneously)
- Cause: Noise on S or R inputs from long floating wires Fix: Add 100nF capacitors from each latch input to GND to filter noise. Keep S and R wires short.
- Two different NOR gates give different outputs for same inputs
- Cause: One gate is damaged (common when inputs were shorted to high-voltage) Fix: Use a multimeter to verify both inputs and the output of each gate independently. Replace the IC if one gate is non-functional.
Frequently asked questions
What is the truth table for a NOR gate circuit diagram?
A 2-input NOR gate outputs 1 only when both A and B are 0. For inputs 01, 10, and 11 the output is 0. The NOR gate has exactly one HIGH output row — the exact complement of OR.
Which IC is used for a NOR gate?
The 7402 (or 74LS02) is the standard TTL quad 2-input NOR gate in a 14-pin DIP. The CMOS equivalent is 74HC02 or CD4001B.
Why is the NOR gate called a universal gate?
Because all Boolean logic functions (AND, OR, NOT, NAND, XOR) can be implemented using only NOR gates. This makes it interchangeable with NAND gates for any digital design.
What is the Boolean expression for a NOR gate?
Y = (A + B)'. By De Morgan's theorem this equals A' · B': the output is 1 only when both inputs are 0.
How is a NOR gate different from a NAND gate?
NOR is the complement of OR (output HIGH only when all inputs are LOW), while NAND is the complement of AND (output LOW only when all inputs are HIGH). In CMOS, NOR uses series PMOS (slower); NAND uses series NMOS (faster).
How do you build an SR latch with NOR gates?
Cross-couple two NOR gates: connect the output of NOR1 to one input of NOR2, and the output of NOR2 back to one input of NOR1. The free inputs are Set (S) and Reset (R). S=1 sets Q=1; R=1 resets Q=0.
What is the pin-out difference between 7402 NOR and 7400 NAND?
In the 7402, outputs are on the outer pins (1, 4, 10, 13) and inputs are on the inner pins, reversed from the 7400 where inputs are outer and outputs inner for each gate. Always verify the datasheet before wiring.