NAND Gate Circuit Diagram: Boolean Logic, Truth Table & Universal Gate
This is a free printable nand gate circuit diagram: download the diagram as SVG or open it and print to paper or PDF.
A NAND gate produces a LOW output only when ALL inputs are HIGH — the inverse of an AND gate. Its Boolean expression for two inputs is Y = (A · B)' (NOT AND). The NAND gate is a universal gate: any Boolean function, including AND, OR, NOT, and XOR, can be built using only NAND gates, making it the most widely used gate in digital IC families.
The NAND gate is a logical AND followed immediately by an inversion (NOT). For two inputs A and B, the Boolean expression is Y = (AB)' = A' + B' (by De Morgan's theorem). This equivalence between NAND and the OR-of-complements form is important for logic minimisation.
Truth table: when A=0, B=0, Y=1; when A=0, B=1, Y=1; when A=1, B=0, Y=1; and only when A=1, B=1, Y=0. The single LOW output row — when all inputs are HIGH — is the defining characteristic of a NAND gate. Compare this to the AND gate, which has only one HIGH row.
Logic symbol: the NAND gate symbol is identical to the AND gate's D-shaped body, but with a small circle (bubble) at the output. The bubble indicates inversion, so the symbol reads 'AND, then invert.' In IEC notation the body is rectangular with an ampersand (&) label and an inversion circle on the output.
Transistor-resistor logic (TTL structure): in the classic TTL 7400, the NAND function is implemented with a multi-emitter input transistor. Both emitters act as the input nodes. If either emitter is pulled LOW, current is diverted away from the base-collector path that would turn on the output transistor, so the output stays HIGH. Only when both emitters are driven HIGH does current flow through the base into the output stage, saturating the output transistor and pulling the output LOW. This elegant multi-emitter structure makes TTL NAND gates inherently fast and power-efficient.
Discrete two-transistor NAND: connect NPN transistors Q1 and Q2 in series between Vcc (through pull-up resistor R_C ≈ 1kΩ) and GND. Input A drives Q1's base through R_B1 (10kΩ); input B drives Q2's base through R_B2 (10kΩ). Take output at the Q1/Q2 collector junction (between the two transistors). When both Q1 and Q2 are saturated (both inputs HIGH), the output is pulled LOW. If either transistor is cut off, the output is pulled HIGH through R_C — giving NAND behaviour.
Integrated circuit: the 7400 is the original quad 2-input NAND gate in TTL, one of the most produced digital ICs ever. Low-power Schottky version: 74LS00. CMOS version: 74HC00. The 4-input NAND is the 7420; the 8-input NAND is the 7430. Package: 14-pin DIP. Pin assignments: gate 1 — pins 1, 2 inputs, pin 3 output; gate 2 — pins 4, 5 inputs, pin 6 output; gate 3 — pins 9, 10 inputs, pin 8 output; gate 4 — pins 12, 13 inputs, pin 11 output. Vcc pin 14, GND pin 7.
Universal gate constructions using 7400: - NOT gate: tie both inputs together. Y = (A · A)' = A' - AND gate: NAND output fed into a NOT (tied-input NAND). Two NAND gates. - OR gate: invert each input with tied-input NANDs, then NAND the results. Three NAND gates. Y = (A' · B')' = A + B by De Morgan. - NOR gate: OR construction plus another tied-input NAND inverter. Four NAND gates.
NAND gates appear in virtually all digital systems: microprocessors use NAND-heavy cell libraries because NAND is faster and smaller than NOR in CMOS technology; SRAM cells use cross-coupled NAND latches; input protection and debounce circuits frequently use NAND-based SR latches.
Experiment with NAND gates in the Circuit Diagram Maker free browser editor — build all four universal constructions on a single canvas and verify each truth table interactively.
How to wire nand gate circuit diagram
- Obtain a 7400 IC The 7400 quad 2-input NAND gate is widely available and inexpensive. Collect a breadboard, 5V supply, two push-buttons, 10kΩ pull-down resistors, 470Ω resistor, and an LED.
- Power the IC Insert the 7400 into the breadboard. Connect pin 14 to +5V and pin 7 to GND. Add a 100nF ceramic capacitor between Vcc and GND directly at the IC pins.
- Wire input A Connect a push-button from +5V to pin 1 with a 10kΩ pull-down from pin 1 to GND. This gives a clean LOW when the button is released.
- Wire input B Repeat the same circuit for pin 2 (input 1B).
- Connect output LED Wire pin 3 (output 1Y) through a 470Ω resistor to the LED anode; cathode to GND. The LED should be ON at power-up (both inputs LOW → output HIGH).
- Test all four input combinations Press neither button (00→LED on), each button individually (01, 10→LED on), then both simultaneously (11→LED off). The LED extinguishes only when both are pressed.
- Build NOT from NAND On gate 2 (pins 4, 5, 6), wire pins 4 and 5 together to form a single input. Connect a signal to both tied pins; read the inverted output on pin 6 — confirming universal gate property.
Specifications
| A=0, B=0 | Y=1 |
|---|---|
| A=0, B=1 | Y=1 |
| A=1, B=0 | Y=1 |
| A=1, B=1 | Y=0 |
| Boolean expression | Y = (A · B)' = A' + B' |
| TTL IC (2-input) | 7400 / 74LS00 |
| CMOS IC (2-input) | 74HC00 / CD4011B |
| 4-input NAND TTL IC | 7420 |
| 8-input NAND TTL IC | 7430 |
| Supply voltage (TTL) | 5V ±5% |
| Propagation delay (74LS00) | 9 ns typical |
Safety warnings
- TTL IC inputs should never be driven from voltages above Vcc + 0.5V — even a brief positive spike above 5.5V can inject charge into the substrate and latch up the device.
- When powering down the circuit, remove the logic signal sources before removing the supply voltage to prevent reverse-biasing the IC's ESD protection diodes.
Tools needed
- 7400 or 74LS00 quad NAND gate IC
- Breadboard and jumper wires
- 5V DC power supply
- Digital multimeter
- LED and 470Ω resistor
- 10kΩ pull-down resistors and 100nF decoupling capacitor
Common mistakes
- Confusing 7400 (NAND) with 7402 (NOR): both are quad 14-pin DIPs but have opposite logic. Always verify the part number before use.
- Leaving unused NAND inputs floating: unlike AND gates where a floating input may read HIGH, TTL NAND floating inputs are unreliable. Always tie unused inputs HIGH (to Vcc via 1kΩ) to prevent spurious LOW outputs.
- Not accounting for the inversion when replacing AND with NAND: a direct one-for-one swap of AND gates with NAND gates changes the logic function. You must add a NAND-as-NOT inverter on the output to restore the intended AND behaviour.
- Overloading a single NAND output with too many fan-in loads: the 74LS00 output can drive 10 LS-TTL loads. Exceeding this causes voltage level degradation and logic errors.
Troubleshooting
- Output always LOW (never goes HIGH)
- Cause: One or both input pins are stuck HIGH due to a pull-up short or miswiring Fix: Check both input pins with a multimeter. Verify pull-down resistors are correctly connected from each input to GND.
- NAND gate acts like a buffer (output follows input)
- Cause: One input is tied permanently HIGH, reducing the 2-input NAND to a single-input NOT; if then both inputs tied together it becomes NOT Fix: Verify both inputs are independently driven. Check for accidental shorts between the two input pins.
- IC overheating
- Cause: Output shorted to GND while output is HIGH, causing excessive sink current Fix: Remove power immediately. Inspect the output net for short circuits. Add a 100Ω series resistor on the output to limit fault current during debugging.
Frequently asked questions
What is the truth table for a NAND gate circuit diagram?
A 2-input NAND gate outputs 0 only when both A and B are 1. For all other input combinations (00, 01, 10) the output is 1. This is the complement of the AND gate truth table.
Which IC number is used for a NAND gate?
The 7400 (or 74LS00) is the standard TTL quad 2-input NAND gate in a 14-pin DIP. The CMOS equivalent is 74HC00 or CD4011B.
Why is the NAND gate called a universal gate?
Because any Boolean logic function — AND, OR, NOT, NOR, XOR, XNOR — can be implemented using only NAND gates. This universality makes NAND the preferred gate in digital VLSI design.
What is the Boolean expression for a NAND gate?
Y = (A · B)'. By De Morgan's theorem this equals Y = A' + B': the output is HIGH if at least one input is LOW.
How do you make an AND gate from NAND gates?
Feed the output of a 2-input NAND gate (pins 1, 2, 3 of a 7400) into a second NAND gate wired as a NOT (both inputs tied, e.g. pins 4, 5 → pin 6). The result is double negation: Y = ((AB)')' = AB.
What is the difference between NAND and NOR gates?
NAND outputs 0 only when all inputs are 1; NOR outputs 0 when any input is 1. NAND is preferred in CMOS because pull-down networks (NMOS series) are naturally faster than pull-up networks (PMOS series).
How many NAND gates does a 7400 IC contain?
Four independent 2-input NAND gates sharing the Vcc (pin 14) and GND (pin 7) supply pins, using the remaining 12 pins for gate inputs and outputs.