OR Gate Circuit Diagram: Boolean Logic, Truth Table & IC Realisation
This is a free printable or gate circuit diagram: download the diagram as SVG or open it and print to paper or PDF.
An OR gate outputs HIGH (1) whenever at least one of its inputs is HIGH. It implements the Boolean OR operation expressed as Y = A + B. OR gates are essential in digital logic for flag detection, interrupt arbitration, and combinational sum-of-products networks.
The OR gate is the logical disjunction operator. For a two-input gate the Boolean expression is Y = A + B, where the plus sign (+) denotes OR, not arithmetic addition. The output is LOW only when every input is simultaneously LOW; a single HIGH input is sufficient to drive the output HIGH.
Truth table: when A=0 and B=0, Y=0 (the only LOW output row). When A=0 and B=1, Y=1; when A=1 and B=0, Y=1; and when A=1 and B=1, Y=1. This '0 only when all inputs are 0' pattern is how an OR gate is instantly recognised.
Logic symbol: the OR gate uses a curved-shield body with two concave input lines and a pointed output. The curvature distinguishes it from the straight-sided AND gate. In IEC rectangular notation the symbol contains the label '≥1', meaning 'output is 1 when the weighted sum of inputs is ≥1'.
Diode-resistor logic (DRL): two diodes D1 and D2 have their anodes connected to inputs A and B respectively, and their cathodes tied together at the output node. A pull-down resistor R connects the output node to GND. When either input is HIGH, the corresponding diode conducts and raises the output to approximately VHigh − 0.7V (one diode drop). When both inputs are LOW the diodes are reverse-biased and the pull-down holds the output LOW. DRL OR is simple and requires no transistors, but the diode voltage drop degrades logic levels in cascaded stages.
Transistor realisation: connect two NPN BJTs Q1 and Q2 in parallel — both collectors tied together to Vcc through a pull-up resistor R_C, and both emitters tied to GND. Input A drives the base of Q1; input B drives the base of Q2. If either transistor saturates (driven by a HIGH input) the output at the collector node is pulled LOW — this is a negative-logic OR (i.e., NOR). Inverting that output gives the true OR. Alternatively, using PNP transistors with inputs at the emitter gives a direct positive-logic OR.
Integrated circuit: the standard TTL OR gate IC is the 7432 (quad 2-input OR gates, 14-pin DIP). The low-power Schottky version is the 74LS32. CMOS equivalents include the 74HC32 and CD4071B. Pinout follows the same quad-gate convention as the 7408: gate 1 uses pins 1, 2, 3; gate 2 uses pins 4, 5, 6; gate 3 uses pins 9, 10, 8; gate 4 uses pins 12, 13, 11. Power: Vcc on pin 14, GND on pin 7.
OR gate applications: OR gates detect whether any one of several alarm flags is active. They are used in the carry-output logic of parallel adders, in parity generators, and in RISC processor condition-code logic. A 3-input OR gate (Y = A + B + C) outputs HIGH if any of the three conditions is active.
OR from universal gates: an OR gate can be synthesised from three NAND gates or three NOR gates, confirming the universality of both NAND and NOR. Using NAND gates: Y = (A NAND A) NAND (B NAND B) — double inversion on each input followed by a NAND produces OR by De Morgan's theorem.
Ready to try it yourself? Drop OR gate symbols into the free Circuit Diagram Maker editor, attach toggle switches to the inputs and an LED to the output, and step through every input combination to confirm the truth table in real time.
How to wire or gate circuit diagram
- Gather components Obtain a 7432 quad OR gate IC, breadboard, 5V supply, two push-button switches, two 10kΩ pull-down resistors, one 470Ω resistor, and an LED.
- Power the IC Insert the 7432 into the breadboard. Connect pin 14 to +5V and pin 7 to GND. Add a 100nF ceramic decoupling capacitor between Vcc and GND close to the IC.
- Wire input A Connect a push-button between +5V and pin 1 (input 1A). Add a 10kΩ pull-down resistor from pin 1 to GND to ensure a clean LOW when the button is released.
- Wire input B Repeat the same push-button and pull-down arrangement for pin 2 (input 1B).
- Connect output LED Run a wire from pin 3 (output 1Y) through a 470Ω resistor to the LED anode; connect the LED cathode to GND.
- Test all four combinations Press neither button (00→LED off), each button alone (01 and 10→LED on), then both buttons (11→LED on). The LED should be off only when both buttons are released.
- Extend to three inputs Chain gate outputs: feed pin 3 into pin 4 (second gate input A) together with a third switch on pin 5, and read the 3-input OR result at pin 6.
Specifications
| A=0, B=0 | Y=0 |
|---|---|
| A=0, B=1 | Y=1 |
| A=1, B=0 | Y=1 |
| A=1, B=1 | Y=1 |
| Boolean expression | Y = A + B |
| TTL IC (2-input) | 7432 / 74LS32 |
| CMOS IC (2-input) | 74HC32 / CD4071B |
| Supply voltage (TTL) | 5V ±5% |
| Supply voltage (CMOS 74HC) | 2V – 6V |
| Propagation delay (74LS32) | 22 ns typical |
| Fan-out (74LS32) | 10 LS-TTL loads |
Safety warnings
- Do not apply voltages above 5.5V to TTL inputs or outputs — even brief transients above this level destroy the internal bipolar junctions.
- Avoid short-circuiting the output pin to GND while it is driven HIGH; TTL outputs can source significant current that may damage the IC output stage.
Tools needed
- 7432 or 74LS32 quad OR gate IC
- Breadboard and jumper wires
- 5V DC power supply
- Digital multimeter
- LED and 470Ω resistor
- 10kΩ pull-down resistors
Common mistakes
- Mixing up 7432 (OR) with 7402 (NOR): the part numbers are close and the packages identical. Double-check the marking on the IC body before inserting.
- Forgetting pull-down resistors on inputs: floating TTL inputs can drift to an indeterminate voltage, causing random output states. Always tie unused inputs to GND through a 10kΩ resistor.
- Using a single shared LED resistor for multiple outputs: each gate output needs its own current-limiting resistor; sharing one resistor causes brightness to vary with how many outputs are HIGH.
- Cascading DRL OR stages without buffering: diode voltage drops accumulate, degrading HIGH levels below the logic threshold. Insert a transistor buffer (emitter follower) between stages.
Troubleshooting
- LED never lights regardless of inputs
- Cause: LED polarity reversed or 7432 not receiving power Fix: Check LED orientation (longer leg to resistor/output). Verify +5V on pin 14 and GND on pin 7 with a multimeter.
- Output always HIGH even with both inputs LOW
- Cause: Input pull-down resistors missing; inputs floating near 1.5V TTL threshold Fix: Add 10kΩ pull-down resistors from each input pin to GND to force a clean 0V LOW.
- IC gets hot within seconds of power-on
- Cause: IC inserted backwards (pin 1 at wrong end) causing supply reversal Fix: Power off immediately. Recheck IC orientation using the notch or dot marking at pin 1, then reinsert correctly.
Frequently asked questions
What is the truth table for an OR gate circuit diagram?
A 2-input OR gate outputs 0 only when both A and B are 0. For all other combinations (01, 10, 11) the output Y is 1. There are three HIGH output rows and one LOW row.
Which IC number is used for an OR gate?
The standard TTL OR gate is the 7432 (or 74LS32), containing four independent 2-input OR gates in a 14-pin DIP. The CMOS equivalent is 74HC32 or CD4071B.
What is the Boolean expression for an OR gate?
Y = A + B, where '+' denotes logical OR (disjunction). For three inputs it extends to Y = A + B + C.
How does an OR gate differ from an XOR gate circuit?
An OR gate outputs 1 when any input is 1, including when both are 1. An XOR gate outputs 1 only when inputs differ; it outputs 0 when both inputs are 1.
Can you build an OR gate from NOR gates?
Yes. Feed the output of a 2-input NOR gate into the inputs of a second NOR gate wired as an inverter. This double-inversion produces Y = A + B by De Morgan's theorem.
What is the diode-resistor logic implementation of an OR gate?
Two diodes with anodes at inputs A and B, cathodes joined at the output node, and a pull-down resistor from the output to GND. Any HIGH input forward-biases its diode and raises the output to near VHigh.
Why does an OR gate output 1 when both inputs are 1?
The OR gate implements logical disjunction: 'true if at least one input is true.' When both inputs are HIGH both diodes (or transistors) conduct simultaneously, both contributing to the HIGH output.