Decoder Circuit Diagram: How a 2-to-4 Binary Decoder Works
This is a free printable decoder circuit diagram: download the diagram as SVG or open it and print to paper or PDF.
A decoder is a combinational logic circuit that converts a binary code of n input lines into a maximum of 2ⁿ unique output lines, asserting exactly one output HIGH for each input combination. The 2-to-4 line decoder accepts two binary inputs (A and B) and activates one of four outputs (Y0–Y3) based on the combined state. Decoders are fundamental building blocks in memory address decoding, seven-segment displays, and demultiplexing applications.
A 2-to-4 binary decoder has two input lines, A (LSB) and B (MSB), and four output lines Y0, Y3. Each output corresponds to one unique minterm of the two inputs. The Boolean expressions for the four outputs are:
Y0 = B'A' (active when B=0, A=0) Y1 = B'A (active when B=0, A=1) Y2 = BA' (active when B=1, A=0) Y3 = BA (active when B=1, A=1)
Notice that each expression is a product term (AND of literals), and exactly one output is HIGH for any given input combination while all others remain LOW. This property makes decoders ideal for selecting exactly one device or memory bank from many.
At the gate level, implementing a 2-to-4 decoder requires two NOT gates (one for each input to generate the complements A' and B') and four 2-input AND gates. NOT gate A' and NOT gate B' are connected to the appropriate AND gate inputs to form each minterm. For example, AND gate Y0 receives inputs B' and A', while AND gate Y3 receives B and A directly.
In practice, the 74HC139 dual 2-to-4 decoder/demultiplexer is the standard TTL/CMOS choice. It includes an active-LOW enable pin (E̅); when E̅ is HIGH, all outputs are forced HIGH (inactive in active-LOW output convention). With active-LOW outputs, the selected line goes LOW and all others remain HIGH — the complement of the active-HIGH convention described above. The 74HC138 is a 3-to-8 decoder and the 74HC154 is a 4-to-16 decoder, both following the same design principle extended to more inputs.
A decoder with an enable input can also serve as a demultiplexer: connect the data line to the enable pin and use the select inputs (A, B) to route the data to one of the four outputs. This dual function makes the 74HC139 especially versatile.
For a three-input (3-to-8) decoder like the 74HC138, the eight outputs cover all minterms of three variables (A, B, C), giving Y0 = C'B'A' through Y7 = CBA. The same AND-NOT construction scales accordingly, using three NOT gates and eight 3-input AND gates.
Decoders are also used to drive seven-segment LED displays. A BCD-to-7-segment decoder (such as the 7447) takes a 4-bit BCD input and drives the a–g segments of the display to render digits 0–9. Internally it uses a combination of NAND, NOR, and AND gates to implement the required segment logic.
When building a decoder on a breadboard, start with the inverters for A and B, route the complement signals alongside the true signals, then wire each AND gate to the appropriate true/complement pair. Verify each output with an LED or logic probe by stepping through the four input combinations in order. You can simulate the full 2-to-4 decoder instantly in the free circuit editor at circuitdiagrammaker.com by placing two NOT gates and four AND gates and connecting them as described.
How to wire decoder circuit diagram
- Identify inputs and outputs Label your two input lines A (LSB) and B (MSB) and four output lines Y0–Y3 on paper or in the schematic editor.
- Generate complements Place a NOT gate for each input to produce A' and B'. These six signals (A, A', B, B') are the building blocks for all four minterms.
- Wire the AND gates Connect four 2-input AND gates: Y0←(B', A'), Y1←(B', A), Y2←(B, A'), Y3←(B, A) following the Boolean expressions.
- Add power and enable logic If using 74HC139, connect pin 1 (E̅) to GND to enable the IC permanently, or tie it to a control signal for selective activation.
- Connect output indicators Attach an LED with a 330 Ω current-limiting resistor to each output to visually verify which output is selected.
- Test all input combinations Step through B=0,A=0 through B=1,A=1 and confirm exactly one output LED lights for each combination.
- Simulate before building Use the free editor at circuitdiagrammaker.com to simulate the decoder and validate the truth table before committing to hardware.
Specifications
| Inputs (B=0, A=0) | Y0=1, Y1=0, Y2=0, Y3=0 |
|---|---|
| Inputs (B=0, A=1) | Y0=0, Y1=1, Y2=0, Y3=0 |
| Inputs (B=1, A=0) | Y0=0, Y1=0, Y2=1, Y3=0 |
| Inputs (B=1, A=1) | Y0=0, Y1=0, Y2=0, Y3=1 |
| Boolean Y0 | B'·A' |
| Boolean Y1 | B'·A |
| Boolean Y2 | B·A' |
| Boolean Y3 | B·A |
| Gate count (2-to-4) | 2× NOT + 4× 2-input AND |
| Standard IC (2-to-4) | 74HC139 (dual, active-LOW outputs) |
| Standard IC (3-to-8) | 74HC138 |
| Supply voltage (74HC) | 2 V – 6 V |
| Propagation delay (74HC139) | ~7 ns at 5 V |
Safety warnings
- Always power off the breadboard before rewiring to prevent accidental short circuits that could damage the IC.
- Ensure current-limiting resistors are installed on all LED outputs; directly connecting LEDs to IC outputs without resistors can exceed the 25 mA per-pin current limit and destroy the device.
Tools needed
- 74HC139 dual 2-to-4 decoder IC (or discrete NOT + AND gates: 74HC04 and 74HC08)
- Breadboard and jumper wires
- 5 V regulated power supply or USB-to-breadboard adapter
- 4× LEDs and 4× 330 Ω resistors for output indicators
- Logic probe or multimeter for signal verification
- circuitdiagrammaker.com for schematic simulation
Common mistakes
- Swapping A and B input connections, which shifts the selected output by one position and produces an incorrect truth table.
- Forgetting to connect the active-LOW enable pin (E̅) of 74HC139 to GND, leaving all outputs inactive regardless of input.
- Using 2-input AND gates for a 3-to-8 decoder instead of 3-input AND gates, producing incorrect output combinations.
- Neglecting pull-up or pull-down resistors on unused input pins, causing floating inputs and spurious output glitches.
- Confusing active-HIGH and active-LOW output conventions when reading a 74HC139 datasheet, leading to inverted logic in the design.
Troubleshooting
- More than one output is active simultaneously
- Cause: Input lines are connected to the same node or a wire is shorted between two AND gate inputs. Fix: Trace each AND gate input back to its unique true or complement signal and verify no unintended connections exist.
- No output is ever active
- Cause: Enable pin (E̅) is left floating HIGH or supply voltage is missing. Fix: Tie E̅ directly to GND and verify VCC and GND connections on the IC.
- Outputs do not match the expected truth table
- Cause: A and B inputs are swapped or complement signals are cross-wired. Fix: Use a logic probe to measure each NOT gate output and confirm A' goes LOW when A is HIGH, then re-trace AND gate wiring.
Frequently asked questions
What is a decoder circuit diagram and how does it work?
A decoder circuit diagram shows how binary input lines are connected through NOT and AND gates so that exactly one output is HIGH for each unique input combination, effectively converting a binary address into a one-hot selection signal.
What is the truth table for a 2-to-4 decoder?
For inputs B and A: (0,0)→Y0=1; (0,1)→Y1=1; (1,0)→Y2=1; (1,1)→Y3=1. All other outputs are 0 in each row.
Which IC number is used for a 2-to-4 decoder?
The 74HC139 is the standard dual 2-to-4 decoder/demultiplexer IC with active-LOW outputs. The older TTL equivalent is the 74LS139.
How many AND gates are needed for a 3-to-8 decoder?
A 3-to-8 decoder requires eight 3-input AND gates plus three NOT gates, giving a total of eight output minterms.
What is the difference between a decoder and a demultiplexer?
Structurally they are identical circuits; when the enable pin is used as a data input and the address lines select the output, the decoder acts as a demultiplexer routing one signal to one of many outputs.
Why does the 74HC138 have active-LOW outputs?
Active-LOW outputs allow multiple decoders to be cascaded using AND-wired (open-collector) connections and reduce power consumption because outputs sink current only when selected.
Can a decoder be used to implement any Boolean function?
Yes. Because a decoder generates all minterms of its input variables, any Boolean function of those variables can be realised by OR-ing the appropriate decoder outputs corresponding to the function's ON-set minterms.