Full Adder Circuit Diagram: Sum, Carry Equations, Truth Table & Gate-Level Build
This is a free printable full adder circuit diagram: download the diagram as SVG or open it and print to paper or PDF.
A full adder adds three 1-bit inputs — A, B, and a Carry-in (Cin) — producing a Sum (S) and a Carry-out (Cout). The equations are S = A ⊕ B ⊕ Cin and Cout = AB + Cin(A ⊕ B). Unlike a half adder, the full adder accepts a carry from a previous bit position, making it the essential unit of multi-bit binary adders and ALUs.
The full adder extends the half adder by accepting a third input, the carry-in bit Cin, which represents the carry produced by the previous less-significant bit position.
Boolean equations: Sum S = A ⊕ B ⊕ Cin. Carry-out Cout = AB + Cin(A ⊕ B) = AB + BCin + ACin. The Cout equation has three product terms because Cout is 1 whenever at least two of the three inputs are 1.
Truth table (8 rows for 3 inputs): - A=0, B=0, Cin=0 → S=0, Cout=0 (0+0+0=0) - A=0, B=0, Cin=1 → S=1, Cout=0 (0+0+1=1) - A=0, B=1, Cin=0 → S=1, Cout=0 (0+1+0=1) - A=0, B=1, Cin=1 → S=0, Cout=1 (0+1+1=2=10₂) - A=1, B=0, Cin=0 → S=1, Cout=0 (1+0+0=1) - A=1, B=0, Cin=1 → S=0, Cout=1 (1+0+1=2=10₂) - A=1, B=1, Cin=0 → S=0, Cout=1 (1+1+0=2=10₂) - A=1, B=1, Cin=1 → S=1, Cout=1 (1+1+1=3=11₂) Cout is HIGH whenever two or more inputs are HIGH — a majority-vote function.
Gate-level schematic (two-stage approach using half adders): implement the full adder as two cascaded half adders plus an OR gate. - Half adder 1: inputs A and B → intermediate Sum S1 = A⊕B, intermediate Carry C1 = AB - Half adder 2: inputs S1 and Cin → final Sum S = S1⊕Cin = A⊕B⊕Cin, intermediate Carry C2 = S1·Cin - Final Cout: OR of C1 and C2 → Cout = C1 + C2 = AB + Cin(A⊕B) Component count: 2 XOR gates, 2 AND gates, 1 OR gate = 5 gates total.
Alternative NAND-only full adder: using nine 2-input NAND gates, the full adder can be implemented without XOR, AND, or OR gates. The derivation follows from NAND-only half adder constructions (5 NANDs each) sharing the intermediate node, but with careful optimisation the total reduces to 9 NANDs.
IC implementation: individual-gate approach uses a 7486 (for XOR gates), a 7408 (for AND gates), and a 7432 (for the OR gate). For practical multi-bit designs, the 74283 is a 4-bit binary full adder IC that internally implements four full adder stages with carry lookahead. Its inputs are A[3:0], B[3:0], and C0 (carry-in to bit 0). Outputs are S[3:0] and C4 (carry-out from bit 3). Pinout is a 16-pin DIP. Two 74283 ICs can be cascaded for 8-bit addition by connecting C4 of the lower IC to C0 of the upper.
Ripple-carry adder: chain N full adders, passing Cout of each stage to Cin of the next. For a 4-bit ripple adder, the carry must propagate through 4 stages — each adding a full-adder delay. For an N-bit adder the worst-case delay is proportional to N. This is the simplest adder architecture; for faster designs, carry lookahead (as in the 74283) or carry-select adders are used.
Full adder in real CPUs: modern CPU ALUs use parallel-prefix carry lookahead adders (e.g., Kogge-Stone or Brent-Kung) that reduce carry propagation to O(log N) stages, but each node is still based on the full adder's generate (G = AB) and propagate (P = A⊕B) terms.
Build a full 4-bit ripple-carry adder by chaining four full adder sub-circuits in the Circuit Diagram Maker free online editor — the cascaded design makes carry propagation visually obvious, and you can step through binary sums interactively.
How to wire full adder circuit diagram
- Gather components Obtain a 7486 (quad XOR), 7408 (quad AND), and 7432 (quad OR) IC, plus a breadboard, 5V supply, three toggle switches (A, B, Cin), two LEDs (Sum and Cout), and 470Ω and 10kΩ resistors.
- Power all ICs Insert all three ICs. Connect pin 14 to +5V and pin 7 to GND on each. Add 100nF decoupling capacitors on each IC's supply pins.
- Build half adder 1 Wire A to pin 1 of the 7486 and pin 1 of the 7408. Wire B to pin 2 of the 7486 and pin 2 of the 7408. Pin 3 of 7486 = S1 (intermediate XOR); pin 3 of 7408 = C1 (intermediate AND/carry).
- Build half adder 2 Wire S1 (7486 pin 3) to pin 4 of the 7486, and Cin (third switch) to pin 5 of the 7486. Pin 6 of 7486 = final Sum S. Wire S1 and Cin to another AND gate (pins 4, 5 of 7408); pin 6 of 7408 = C2.
- OR the two carries Wire C1 (7408 pin 3) to pin 1 of the 7432, and C2 (7408 pin 6) to pin 2 of the 7432. Pin 3 of 7432 = Cout.
- Connect indicator LEDs Connect Sum (7486 pin 6) via 470Ω to Sum LED. Connect Cout (7432 pin 3) via 470Ω to Cout LED. All LED cathodes to GND.
- Verify all 8 input combinations Step through all combinations of A, B, Cin switches and confirm S and Cout match the truth table. Pay special attention to A=1,B=1,Cin=1 which should give S=1 and Cout=1.
Specifications
| A=0,B=0,Cin=0 → S,Cout | S=0, Cout=0 |
|---|---|
| A=0,B=0,Cin=1 → S,Cout | S=1, Cout=0 |
| A=0,B=1,Cin=0 → S,Cout | S=1, Cout=0 |
| A=0,B=1,Cin=1 → S,Cout | S=0, Cout=1 |
| A=1,B=0,Cin=0 → S,Cout | S=1, Cout=0 |
| A=1,B=0,Cin=1 → S,Cout | S=0, Cout=1 |
| A=1,B=1,Cin=0 → S,Cout | S=0, Cout=1 |
| A=1,B=1,Cin=1 → S,Cout | S=1, Cout=1 |
| Sum equation | S = A ⊕ B ⊕ Cin |
| Carry-out equation | Cout = AB + BCin + ACin |
| Gate count (XOR+AND+OR) | 2 XOR + 2 AND + 1 OR = 5 gates |
| 4-bit adder IC | 74283 (carry lookahead) |
Safety warnings
- When wiring three ICs on a single breadboard, ensure all GND pins are connected to the same common ground rail — a missing ground connection on any IC causes erratic logic levels across the whole circuit.
- Always power down before rewiring the Cin cascading wire between stages; connecting Cin while powered can cause a glitch that produces incorrect carry propagation and may corrupt adjacent flip-flop states in a larger system.
Tools needed
- 7486 quad XOR gate IC
- 7408 quad AND gate IC
- 7432 quad OR gate IC
- Breadboard and jumper wires
- 5V DC power supply
- Two LEDs (Sum and Cout) with 470Ω resistors
- Three toggle switches with 10kΩ pull-down resistors
Common mistakes
- Connecting C1 and C2 with AND instead of OR for Cout: students sometimes confuse the carry-out logic. Cout is HIGH when either half adder generates a carry, so it must be OR, not AND.
- Omitting the Cin input entirely: building only a half adder (no Cin) and labelling it a full adder is a common exam error. Always verify the circuit has three inputs.
- Using a single XOR gate for the Sum: the full adder Sum requires A ⊕ B ⊕ Cin, which needs two XOR gates in cascade. A single XOR of only two inputs gives the wrong sum for three-input cases.
- Not tying Cin to GND for LSB position in a ripple adder: if the first stage's Cin is left floating, TTL inputs may float to a spurious HIGH, giving incorrect results for the least-significant bit.
Troubleshooting
- Cout LED never lights
- Cause: OR gate output (Cout) not connected, or both AND gate carry outputs C1 and C2 miswired Fix: Probe C1 and C2 separately with a multimeter. Verify pin 3 of the 7432 is connected and that both C1 and C2 feed the OR gate inputs.
- Sum incorrect for A=1,B=1,Cin=1 (expect S=1)
- Cause: Second XOR gate inputs not correctly receiving S1 and Cin Fix: Trace S1 (7486 pin 3) and Cin switch to the second XOR gate inputs (7486 pins 4 and 5). Check for loose jumper connections.
- Random outputs when switching inputs
- Cause: Missing pull-down resistors causing floating input levels during switch transitions Fix: Add 10kΩ pull-down resistors on all three input switch lines (A, B, Cin) to ensure clean LOW states when switches are open.
Frequently asked questions
What is the truth table for a full adder circuit diagram?
A full adder has 8 rows (3 inputs × 2 states). Cout is 1 when two or more of A, B, Cin are 1 (a majority function). Sum equals 1 when an odd number of inputs are 1.
What is the difference between a half adder and full adder circuit?
A half adder adds two 1-bit inputs (no carry-in); a full adder adds three 1-bit inputs (A, B, and Carry-in). Full adders can be chained for multi-bit addition; half adders cannot.
What are the Boolean equations for a full adder?
Sum S = A ⊕ B ⊕ Cin. Carry-out Cout = AB + BCin + ACin. The carry equation computes a majority function: Cout is 1 when at least two inputs are 1.
How many gates does a full adder use?
The two-half-adder implementation uses 5 gates: 2 XOR, 2 AND, and 1 OR. A NAND-only implementation uses 9 NAND gates. The 74283 IC contains four full adders with carry lookahead internally.
Which IC is a full adder?
The 74283 (or 74LS283) is a 4-bit binary full adder IC with internal carry lookahead. It adds two 4-bit inputs plus a carry-in and produces a 4-bit sum plus carry-out.
How do you cascade full adders for multi-bit addition?
Connect the Cout of each full adder stage to the Cin of the next more-significant stage. For a 4-bit adder, the first stage Cin is tied to GND (0). This forms a ripple-carry adder.
What is a ripple-carry adder and what are its limitations?
A ripple-carry adder chains N full adders. The carry must propagate through every stage serially, so the worst-case delay grows linearly with N. For 32-bit or 64-bit addition, carry lookahead (as in the 74283) or parallel-prefix architectures are used instead.