P-Channel MOSFET Symbol
Definition: The P-Channel MOSFET symbol represents a P-channel enhancement-mode (or depletion-mode) Metal-Oxide-Semiconductor Field-Effect Transistor, designated Q in schematics, that conducts current from Source to Drain when its Gate voltage is sufficiently negative with respect to the Source (V_GS < V_th, where V_th is negative), per IEC 60617-05 and ANSI/IEEE 315-1975.
Also known as: P-channel MOSFET, PMOS transistor, P-MOSFET, P-channel FET, pMOS, P-channel enhancement MOSFET, PFET.
What the P-Channel MOSFET symbol means
The P-Channel MOSFET symbol denotes a field-effect transistor in which the conducting channel is formed by holes (positive charge carriers) in a P-type semiconductor region. The Gate controls channel conductivity: applying a sufficiently negative voltage to the Gate (relative to the Source) creates the conducting channel between Drain and Source, allowing current to flow.
In circuit diagrams the P-Channel MOSFET symbol appears in high-side switch circuits (where the source connects to the positive supply), CMOS logic gates (where PMOS pulls the output high), analog switches, and power management circuits. The three terminals — Gate, Drain, and Source — control and carry the switched current.
How to identify the P-Channel MOSFET symbol
The P-Channel MOSFET symbol is drawn with a vertical line representing the channel, a horizontal Gate terminal approaching the channel but separated by a gap (representing the insulating oxide), and separate Drain and Source connections to the channel. The key feature that distinguishes PMOS from NMOS is the direction of the body diode arrow: in the PMOS symbol, the arrow on the bulk/body terminal (or the inversion arrow near the Gate) points FROM the channel TOWARD the Source (i.e., pointing inward toward the body, opposite to NMOS where it points outward). For enhancement-mode PMOS, the channel line is shown dashed (broken) to indicate the normally-off state. The Source terminal connects to the more positive supply rail in high-side switch topologies.
Function in a circuit
A P-Channel MOSFET operates as a voltage-controlled switch or amplifier using a P-type conducting channel. When V_GS = 0 (Gate at same voltage as Source), the enhancement-mode PMOS is OFF (no channel, no Drain-Source current). When V_GS is more negative than the threshold voltage V_tp (typically −1 to −4 V for logic-level devices, −2 to −5 V for power MOSFETs), the P-channel forms between Drain and Source and current flows from Source to Drain (conventional current direction). The on-state resistance R_DS(on) determines conduction losses; gate charge Q_g determines switching speed. The body diode (source-anode to drain-cathode in PMOS) allows reverse current conduction.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-05 (semiconductors and electron tubes) defines the MOSFET graphic symbol. The P-channel enhancement-mode MOSFET is distinguished by the arrow direction on the bulk/channel indicating P-type material, and a broken channel line indicating normally off. IEC 60747-3 covers discrete field-effect transistors including MOSFET parameters and test methods. |
|---|---|
| ANSI/IEEE 315 | ANSI/IEEE 315-1975 (graphic symbols for electrical and electronics diagrams) defines the MOSFET symbol. The P-channel type is identified by the direction of the inversion indicator arrow on the Gate or the body diode arrow pointing from body to channel. IEEE 315 uses the same symbol body as IEC 60617-05 but the arrow direction convention requires careful reading. |
| Key difference | In both IEC 60617-05 and ANSI/IEEE 315-1975, the PMOS symbol is visually similar to NMOS but with the body diode arrow reversed (pointing from Source to Body in PMOS, or from Body to Drain in NMOS — both indicating the P-N junction orientation). In NMOS the arrow points toward the channel (into the device); in PMOS the arrow points away from the channel (out from the device). This arrow direction is the sole visual differentiator between NMOS and PMOS symbols. |
Terminals / pins
| Pin | Name |
|---|---|
| gate | Gate |
| drain | Drain |
| source | Source |
Typical values
Threshold voltage V_tp: typically −1 to −4 V (logic-level PMOS, e.g., BSS84), −2 to −5 V (standard power PMOS); drain-source voltage V_DSS: 12–1000 V; continuous drain current I_D: 0.1–200 A; on-resistance R_DS(on): 5 mΩ – 10 Ω (inversely related to V_GS overdrive and device size); gate charge Q_g: 1–500 nC; supply voltage: limited by V_DSS rating.
Where the P-Channel MOSFET symbol is used
- High-side switching: PMOS with Source connected to V+ supply switches load current to ground through the Drain, controlled by a low Gate voltage relative to V+
- CMOS logic gates: PMOS pull-up transistor in CMOS inverters, NAND, and NOR gates pulls the output to V_DD when the input is LOW (Gate near 0 V)
- Power management: PMOS in battery charger circuits, load switches, and power multiplexer ICs controls current flow from a high-side supply rail
- Analog switches and multiplexers: PMOS in CMOS transmission gates (paired with NMOS) provides low on-resistance bidirectional switching for signal routing
- H-bridge motor drivers: PMOS high-side transistors paired with NMOS low-side transistors to drive DC motors in both directions
- Linear regulators: PMOS pass transistors in LDO regulators provide low dropout voltage (V_SD of PMOS is lower than V_CE of bipolar pass transistors)
Example
In a 3.3 V microcontroller high-side load switch circuit, a PMOS transistor (e.g., BSS84, V_tp = −1.5 V) has its Source connected to the 3.3 V supply rail and its Drain connected to a peripheral device. A 10 kΩ pull-up resistor connects Gate to Source (3.3 V). When the microcontroller GPIO drives the Gate LOW (0 V), V_GS = −3.3 V < V_tp, the PMOS switches ON and powers the peripheral. When GPIO is HIGH (3.3 V), V_GS = 0 V, the PMOS switches OFF.
Key facts
- The P-Channel MOSFET symbol (designator Q) is identified by the body diode arrow pointing from Source to Body (outward from the channel), the opposite direction from the NMOS arrow, indicating P-type channel material.
- A P-Channel MOSFET (enhancement mode) is normally OFF when V_GS = 0 and conducts when V_GS is more negative than its threshold voltage V_tp (typically −1 to −4 V).
- The three terminals are Gate (voltage-controlled input), Drain (current output for conventional current from Source to Drain), and Source (connected to the more positive rail in high-side switch configurations).
- IEC 60617-05 and ANSI/IEEE 315-1975 both define the PMOS symbol; the arrow direction (pointing away from the channel in PMOS, toward the channel in NMOS) is the key visual difference between the two types.
- In CMOS logic gates, PMOS transistors form the pull-up network (connecting output to V_DD) and NMOS transistors form the pull-down network (connecting output to GND); both must conduct to complete a logic transition.
- The body diode in a PMOS has its anode at the Source and cathode at the Drain, allowing reverse current flow from Drain to Source even when the MOSFET is off (important in H-bridge and buck converter topologies).
- R_DS(on) (on-state Drain-Source resistance) is a critical power PMOS parameter: lower R_DS(on) means lower conduction losses; for a 20 A load at R_DS(on) = 25 mΩ, power dissipation is P = I²R = 400 × 0.025 = 10 W.
- PMOS is typically preferred for high-side switches in battery-powered systems because the Gate can be driven directly by the microcontroller without a charge pump, provided the supply voltage is within the device's logic-level V_GS(th) range.
Frequently asked questions
What does the P-Channel MOSFET symbol mean in a circuit diagram?
The P-Channel MOSFET symbol (designator Q) in a circuit diagram represents a voltage-controlled semiconductor switch in which a negative Gate-to-Source voltage (V_GS more negative than V_tp) creates a conducting P-type channel between Drain and Source. The symbol indicates where a high-side switch, CMOS logic pull-up, or power management switch is implemented using a PMOS transistor.
What does the P-Channel MOSFET symbol look like?
The P-Channel MOSFET symbol has a vertical channel line, a Gate terminal separated from the channel by a gap (the oxide), and Drain and Source terminals on the channel. The critical identifier is the body diode arrow pointing FROM the Source TOWARD the channel (outward from the device body) — this is opposite to the NMOS arrow which points inward. For enhancement mode, the channel line is dashed (broken), indicating the normally-off state.
What is the difference between a P-Channel and N-Channel MOSFET symbol?
In the NMOS symbol, the body diode arrow points from the body toward the channel (inward), indicating N-type channel material; in the PMOS symbol, the arrow points from the channel toward the Source (outward), indicating P-type material. NMOS turns on with positive V_GS (Gate more positive than Source); PMOS turns on with negative V_GS (Gate more negative than Source). NMOS is used in low-side switches; PMOS is used in high-side switches.
What are the terminals (pins) on a P-Channel MOSFET?
A P-Channel MOSFET has three terminals: Gate (the voltage-controlled input — applying V_GS < V_tp turns the device on), Drain (one end of the conducting channel — conventional current flows from Source to Drain when on), and Source (connected to the positive supply rail in high-side switch configurations). A fourth internal terminal, the Body/Bulk, is typically internally connected to the Source in discrete power MOSFETs.
How is a P-Channel MOSFET used as a high-side switch?
In a high-side switch, the PMOS Source connects to the positive supply (V+). The load connects between the Drain and ground. A pull-up resistor connects Gate to Source (V+) to keep the device off when the control signal is floating. The microcontroller or driver pulls the Gate LOW (toward ground) to make V_GS negative enough to exceed V_tp, turning the PMOS on and allowing current to flow through the load. When the control signal releases, the pull-up resistor returns Gate to V+, turning the device off.
What is the threshold voltage of a P-Channel MOSFET?
The threshold voltage V_tp of a P-Channel MOSFET is the Gate-to-Source voltage at which the PMOS begins to conduct. V_tp is always negative for enhancement-mode PMOS: typically −1 to −2 V for logic-level PMOS (e.g., BSS84 at −1 V), and −2 to −5 V for standard power PMOS. The device fully turns on when V_GS is 2–3 V more negative than V_tp (e.g., V_GS = −5 V for V_tp = −3 V).
What standard defines the P-Channel MOSFET symbol?
The P-Channel MOSFET symbol is defined in IEC 60617-05 (graphical symbols for diagrams — semiconductors and electron tubes) and ANSI/IEEE 315-1975 (graphic symbols for electrical and electronics diagrams). IEC 60747-3 (discrete field-effect transistors) governs MOSFET parameter definitions and test methods. The component reference designator Q is defined in IEEE 200-1975 and IEC 60750.
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