Shift Register (8-bit) Symbol
Definition: The Shift Register (8-bit) symbol represents a serial-in/parallel-out (SIPO) digital storage register that accepts data serially on a single DATA pin, shifts it through eight internal flip-flops on each CLK rising edge, and presents all eight bits simultaneously on parallel output pins QA–QH when the LATCH pin is pulsed, as defined by IEEE 315 logic-block conventions and exemplified by the industry-standard 74HC595 IC.
Also known as: SIPO shift register, 74HC595, 8-bit serial-to-parallel register, serial-parallel converter, output shift register.
What the Shift Register (8-bit) symbol means
The Shift Register (8-bit) symbol marks a logic building block that converts a serial bit stream into eight parallel output lines. One bit of data is clocked into the first stage on each rising edge of CLK; after eight clock pulses the full 8-bit word is held in the shift register's internal stages. Pulsing the LATCH (storage register clock) transfers all eight bits simultaneously to the parallel outputs QA–QH, updating them atomically.
In a schematic diagram this symbol allows a microcontroller to drive eight outputs using only three GPIO lines — DATA, CLK, and LATCH — greatly reducing pin count for applications such as LED arrays, keypad decoders, and parallel port expanders. Multiple 74HC595-type devices can be daisy-chained by connecting the serial output (QH') of one to the DATA input of the next.
How to identify the Shift Register (8-bit) symbol
The Shift Register (8-bit) symbol is drawn as a rectangular logic block labelled '8-bit Shift Register' or '74HC595'. Input pins on the left side include DATA (serial data in), CLK (shift clock), and LATCH (storage register clock). Power pins VCC and GND appear at the top and bottom respectively. Output pins QA–QH (or Q0–Q7) exit the right side of the block in order from top to bottom. Some representations also show an OE (output enable, active low) and SRCLR (serial clear, active low) pin.
Function in a circuit
The shift register stores a single serial bit per CLK cycle in an 8-stage internal register. After all 8 bits are clocked in, a LATCH pulse copies the internal shift-register contents to the output latch, simultaneously updating all eight parallel outputs QA–QH. The outputs can drive LEDs, relay drivers, or other logic devices directly, with a single microcontroller managing the entire 8-bit bus from three GPIO pins.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 defines graphical symbols for logic elements. An 8-bit shift register is represented as a labelled rectangular logic block with the qualifying symbol SRG8 (shift register, 8 stages) inside, with mode-control inputs on the left and data outputs on the right per IEC 617. |
|---|---|
| ANSI/IEEE 315 | IEEE 315 (ANSI Y32.2) / IEEE Std 91a-1991 represents shift registers as dependency-notation logic blocks. The 8-bit SIPO register uses the SRG8 distinctive shape with SRG (shift register) label and number of stages noted. The 74HC595 pin designations (QA–QH, SER, SRCLK, RCLK) follow the TI/Motorola standard datasheet. |
| Key difference | IEC 60617-12 and IEEE Std 91a-1991 both use the SRG notation for shift registers. IEC labelling uses internal dependency notation; ANSI/IEEE uses pin-function labels on the symbol outline. For the 74HC595 specifically, both standards produce a visually similar block; IEC may add internal arrows showing the shift direction. |
Terminals / pins
| Pin | Name |
|---|---|
| data | DATA |
| clk | CLK |
| latch | LATCH |
| qa | QA |
| qb | QB |
| qc | QC |
| vcc | VCC |
| gnd | GND |
Typical values
Supply voltage: 2.0 V–6.0 V (74HC595). Maximum clock frequency: 25 MHz at 4.5 V supply (74HC595). Output current: ±6 mA per pin (74HC595 standard), 35 mA per pin (74HCT595 with ULN2803 driver). Propagation delay: 15 ns typical at 5 V. Number of stages: 8. Package: DIP-16, SOIC-16, TSSOP-16.
Where the Shift Register (8-bit) symbol is used
- Expanding microcontroller GPIO: driving 8 LEDs, 8 relay channels, or 8 status indicators from 3 GPIO pins
- LED matrix and bar-graph driver: loading row or column data into shift registers to drive LED arrays with minimal MCU wiring
- Keypad and button matrix interface: extending the microcontroller's output count for row-scanning in matrix keyboards
- Seven-segment display multiplexing: loading segment data for each digit sequentially into daisy-chained 74HC595s
- Serial-to-parallel signal conversion in FPGA prototype boards and logic analyser expansion modules
- Industrial PLC I/O expansion: sending 8 digital output states over a 3-wire SPI bus to remote terminal blocks
Example
In an Arduino LED matrix driver schematic, two 74HC595 shift registers are daisy-chained: the DATA, CLK, and LATCH pins of the first device connect to Arduino pins 11, 13, and 10 respectively; the QH' (serial-out) of the first device feeds the DATA input of the second, extending the total output count to 16 using the same three GPIO lines. Sending a 16-bit value with shiftOut() commands fills both devices, and pulsing LATCH updates all 16 parallel outputs simultaneously.
Key facts
- The Shift Register (8-bit) symbol's three control pins are DATA (serial data input), CLK (shift clock — shifts data one stage on each rising edge), and LATCH (storage register clock — transfers all 8 shift-register bits to the parallel outputs simultaneously).
- The 74HC595 is the industry-standard 8-bit SIPO shift register; its pin designations are SER (DATA), SRCLK (CLK), RCLK (LATCH), QA–QH (parallel outputs), and QH' (serial cascade output for daisy-chaining).
- Daisy-chaining N shift registers extends the parallel output count to 8N using the same 3 GPIO lines; data is shifted through all devices and the LATCH pulse updates all outputs simultaneously.
- The LATCH pin separates the shift operation from the output update: the outputs do not change while data is being shifted in, preventing LED or relay glitches during the serial data transfer.
- The 74HC595 output latch holds its state even when the shift-register content is overwritten by new incoming data, allowing the current output state to be maintained while a new 8-bit word is being shifted in.
- An OE (Output Enable, active low) pin on the 74HC595 can tri-state all eight outputs simultaneously, useful for bus sharing or power-down applications, without affecting the shift-register or latch contents.
- The maximum output source/sink current per pin of the 74HC595 is ±6 mA; for driving higher-current loads such as solenoids or motors, a ULN2803 Darlington array or MOSFET driver must be inserted between the shift register outputs and the load.
Frequently asked questions
What does the shift register 8-bit symbol mean in a schematic?
The 8-bit shift register symbol represents a SIPO (serial-in parallel-out) logic device that accepts data one bit at a time on the DATA pin and presents all 8 bits simultaneously on outputs QA–QH when the LATCH pin is pulsed. It is used to expand the number of digital outputs from a microcontroller using only 3 GPIO pins.
What does the shift register symbol look like?
The shift register symbol is a rectangular logic block with DATA, CLK, and LATCH inputs on the left, VCC at the top, GND at the bottom, and eight parallel outputs QA through QH (or Q0–Q7) on the right. The block may be labelled SRG8 per IEC 60617-12 or show the IC part number (e.g. 74HC595).
What are the DATA, CLK, and LATCH pins on a shift register?
DATA is the serial input that feeds one bit into the first flip-flop stage on each rising CLK edge. CLK (shift clock) advances all 8 bits one position along the shift chain each rising edge. LATCH (storage register clock) copies the current 8-bit shift-register content to the parallel output pins QA–QH, updating all outputs simultaneously.
How do I daisy-chain multiple 8-bit shift registers?
Connect the QH' (serial cascade output) of the first shift register to the DATA input of the next. Share CLK and LATCH between all devices. Each CLK pulse shifts data through all devices in the chain; after sending N×8 bits total, a single LATCH pulse updates all N×8 parallel outputs at once.
What is the difference between IEC and ANSI shift register symbols?
IEC 60617-12 uses the SRG8 qualifier label inside a rectangular block with internal dependency-notation arrows. IEEE Std 91a-1991 (ANSI) uses a similar rectangular block with pin-function labels (SER, SRCLK, RCLK, QA–QH). Both conventions identify the same 8-bit SIPO shift-register function.
What is the 74HC595 and why is it used?
The 74HC595 is the most widely used 8-bit SIPO shift register IC, available from multiple manufacturers. It is used because it allows 8 digital outputs to be controlled from 3 GPIO pins, supports daisy-chaining, includes a separate output latch to prevent glitches, and operates from 2 V to 6 V with 25 MHz maximum clock speed.
Can a shift register directly drive LEDs or relays?
The 74HC595 can directly drive LEDs through current-limiting resistors (each output supplies up to ±6 mA). For relay coils, solenoids, or other inductive or high-current loads, a ULN2803 Darlington array or individual MOSFET drivers must be used between the shift register outputs and the load, as the 74HC595 output current is insufficient for these loads.
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