Sigma-Delta ADC Symbol
Definition: The Sigma-Delta ADC symbol represents a high-resolution analogue-to-digital converter that uses oversampling and noise-shaping techniques to achieve 16-bit to 32-bit resolution at low-to-medium sample rates, shown in electronic schematic diagrams with differential analogue inputs (AIN+ and AIN−), a digital data output (DOUT), and a data-ready signal (DRDY), as exemplified by the ADS1256 and similar sigma-delta converter ICs.
Also known as: sigma-delta converter, delta-sigma ADC, ΔΣ ADC, oversampling ADC, high-resolution ADC, ADS1256 equivalent.
What the Sigma-Delta ADC symbol means
The Sigma-Delta ADC symbol marks a converter block that achieves very high bit-resolution (16–32 bits) by sampling the analogue input at a rate far higher than the Nyquist frequency (oversampling) and using a feedback loop that shapes quantisation noise out of the signal band. The resulting bitstream is digitally filtered (decimated) to produce a high-resolution output word at a lower data rate.
In a schematic the symbol identifies a precision measurement front-end. The differential input pair AIN+ and AIN− allows common-mode noise rejection for accurate measurement of small signals such as thermocouple voltages, strain-gauge bridge outputs, or weigh-cell signals. The DOUT pin carries the digital result, and the DRDY pin signals the host processor when a new conversion result is ready.
How to identify the Sigma-Delta ADC symbol
The Sigma-Delta ADC symbol is drawn as a labelled rectangular IC/module block. Differential analogue inputs AIN+ and AIN− appear on the left side. Digital output DOUT and data-ready DRDY pins appear on the right side. Power pins (AVDD, DVDD, AGND, DGND) and serial interface pins (SCLK, CS, DIN/MOSI) may also be shown. The internal sigma-delta modulator is sometimes represented by a small Σ-Δ notation inside the block.
Function in a circuit
A sigma-delta ADC oversamples the analogue input at a rate many times the signal bandwidth, then applies noise shaping using a feedback integrator (the delta modulator) to push quantisation noise to high frequencies outside the signal band. A digital decimation filter removes the high-frequency noise content and averages the oversampled bitstream to produce a high-resolution output word. The result is an ADC with very low noise in the signal band, making it ideal for precision DC and low-frequency measurements.
Standards: IEC vs ANSI
| IEC 60617 | No dedicated IEC 60617 symbol exists for a sigma-delta ADC. IEC 60617 represents A/D converters as labelled rectangular functional blocks (per the general converter block convention in IEC 60617-12). |
|---|---|
| ANSI/IEEE 315 | IEEE 315 / ANSI Y32.2 represents ADC blocks as labelled rectangles with analogue input and digital output designations. IEEE 1241 and IEEE 1057 are the relevant IEEE standards for ADC testing and characterisation. |
| Key difference | Both IEC and ANSI use the same generic ADC block symbol. The sigma-delta architecture is a circuit design technique rather than a distinct symbol type; the Σ-Δ notation inside the block is a convention used by IC manufacturers to indicate the converter architecture. |
Terminals / pins
| Pin | Name |
|---|---|
| ain_p | AIN+ |
| ain_n | AIN- |
| dout | DOUT |
| drdy | DRDY |
Typical values
Resolution: 16-bit to 32-bit (typical for sigma-delta). Output data rate: 2.5 SPS to 30 000 SPS (ADS1256); 1 SPS to 3840 SPS (ADS1232). Input voltage range: ±VREF (ratiometric) or ±2.5 V (fixed). ENOB (effective number of bits): 20–24 bits at low data rates. Supply voltage: 2.7 V–5.25 V (digital); 2.7 V–5.25 V (analogue, separate supply recommended). SPI clock: up to 7.68 MHz (ADS1256).
Where the Sigma-Delta ADC symbol is used
- Precision weigh scales and load-cell amplifiers requiring 20–24-bit resolution to resolve small weight changes
- Thermocouple and RTD temperature measurement using 24-bit sigma-delta ADCs for sub-millikelvin resolution
- Strain-gauge bridge measurement in industrial process weighing and force measurement systems
- Precision DC voltage and current measurement in laboratory instruments and power analysers
- Chemical analysis instruments (pH, conductivity, dissolved oxygen) requiring stable high-resolution DC measurements
- Audio ADCs in professional recording equipment using sigma-delta converters for high dynamic range (24-bit, 192 kHz)
Example
In a precision weigh-scale schematic, the ADS1256 Sigma-Delta ADC symbol is connected with AIN+ to the positive output of a load-cell instrumentation amplifier and AIN− to the negative output, providing differential noise rejection. DOUT connects to the Arduino SPI MISO pin, DRDY to a GPIO interrupt pin, and SCLK/CS to the SPI bus, allowing the microcontroller to poll DRDY and read 24-bit conversion results over SPI for weight calculation.
Key facts
- The Sigma-Delta ADC achieves high resolution (16–32 bits) by oversampling at many times the signal bandwidth and using noise shaping to push quantisation noise out of the signal band, unlike successive-approximation ADCs which sample once per conversion.
- The ADS1256 is a widely used 24-bit sigma-delta ADC with a maximum data rate of 30 kSPS, a programmable gain amplifier (PGA), and an 8-channel multiplexer, making it the reference design for precision measurement applications.
- The differential input pair AIN+ and AIN− (pins ain_p and ain_n in the schematic) enables common-mode rejection, allowing the converter to accurately measure small signals (microvolts) in the presence of large common-mode noise.
- DRDY (data ready, active low) is a critical signal in sigma-delta ADC circuits: the host must wait for DRDY to assert low before reading DOUT; reading before DRDY is asserted yields stale or corrupt data.
- Sigma-delta ADCs require separate analogue (AVDD, AGND) and digital (DVDD, DGND) power planes with decoupling capacitors at each supply pin to prevent digital switching noise from degrading the analogue conversion accuracy.
- The oversampling ratio (OSR) and resulting output data rate are inversely related: higher OSR gives higher effective resolution but lower data rate; the ADS1256 provides 30 kSPS at 20-bit ENOB and 2.5 SPS at 23+ bit ENOB.
- Unlike SAR ADCs, sigma-delta ADCs have a latency of several conversion cycles (the filter group delay) before the output reflects a step change at the input; this must be accounted for in multiplexed measurement systems by inserting settling cycles after switching channels.
Frequently asked questions
What does the sigma-delta ADC symbol mean in a schematic?
The sigma-delta ADC symbol represents a high-resolution analogue-to-digital converter that uses oversampling and noise shaping to achieve 16–32-bit resolution. It converts a differential analogue voltage at AIN+ and AIN− into a high-resolution digital word available on DOUT, with DRDY signalling when a valid result is ready.
What does the sigma-delta ADC symbol look like?
The sigma-delta ADC symbol is a labelled rectangular block. Differential analogue inputs AIN+ (ain_p) and AIN− (ain_n) appear on the left side. DOUT (digital data output) and DRDY (data-ready) appear on the right side. Power, clock, and chip-select pins may also be shown. A Σ-Δ notation inside the block identifies the converter architecture.
What is the difference between a sigma-delta ADC and a SAR ADC?
A SAR (successive-approximation register) ADC samples once per conversion using a binary-search algorithm, achieving 8–16-bit resolution at high speed (up to MSPS rates). A sigma-delta ADC oversamples the input at a high rate and digitally filters the result, achieving 16–32-bit resolution at lower data rates (up to tens of kSPS). Sigma-delta is preferred for precision DC and audio measurements; SAR is preferred for fast, moderate-resolution conversions.
What are the AIN+ and AIN− pins on a sigma-delta ADC symbol?
AIN+ is the positive differential analogue input and AIN− is the negative differential analogue input. The ADC measures the voltage difference (AIN+ − AIN−), which rejects common-mode voltages and interference that appear equally on both inputs, enabling accurate measurement of small sensor signals in electrically noisy environments.
What does the DRDY pin on a sigma-delta ADC do?
DRDY (Data Ready) is an active-low output that asserts low when a complete conversion result is available on DOUT. The host microcontroller must wait for DRDY to go low before initiating an SPI read of the conversion data; reading before DRDY asserts yields the previous result or invalid data.
What resolution does the ADS1256 sigma-delta ADC provide?
The ADS1256 provides 24-bit resolution with an effective number of bits (ENOB) of approximately 23 bits at low data rates (2.5 SPS). At the maximum data rate of 30 000 SPS the ENOB reduces to approximately 20 bits. It includes a programmable gain amplifier (PGA) with gains of 1, 2, 4, 8, 16, 32, and 64.
Why does a sigma-delta ADC need separate analogue and digital power supplies?
Digital switching in the sigma-delta modulator and digital output circuitry generates high-frequency noise on the power supply rails. If the analogue input stage and reference share this noisy supply, the noise is directly added to the measurement, degrading accuracy. Separate AVDD/AGND and DVDD/DGND supply paths, each with local decoupling capacitors, isolate the noise and preserve the ADC's theoretical high resolution.
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