Peak Detector Symbol
Definition: The Peak Detector symbol represents an analog signal-processing circuit block — built around an operational amplifier (op-amp), diode, and hold capacitor — that captures and holds the maximum (peak) voltage value of an input waveform at its output, used in audio level metering, envelope detection, and signal conditioning applications, with terminals In and Out.
Also known as: peak hold circuit, positive peak detector, envelope detector (peak type), sample-and-hold peak, max detector, op-amp peak detector.
What the Peak Detector symbol means
The Peak Detector symbol represents a functional circuit block that tracks an input signal voltage and holds the highest peak voltage achieved at its output. The basic circuit uses a diode (typically a Schottky or signal diode) in the feedback path of an op-amp with a hold capacitor at the output: when the input exceeds the held output voltage, the op-amp charges the capacitor through the diode to the new peak; when the input falls, the diode blocks reverse current and the capacitor retains the peak voltage.
In schematic block diagrams, the peak detector symbol represents this complete functional circuit. Peak detectors appear in audio VU metering (holding peak levels for display), fault detection (capturing transient voltage spikes), envelope following (tracking signal amplitude), and precision analog measurement systems where the maximum value of a waveform must be captured and held for processing.
How to identify the Peak Detector symbol
The Peak Detector symbol is drawn as a rectangular block labelled 'Peak Detector' or 'PEAK HOLD' with two terminals: In (signal input, on the left) and Out (peak-held output, on the right). Inside or beside the block, a small waveform icon with a dashed hold-line at the peak may indicate the function. In more detailed schematics, the peak detector is shown as its constituent components: an op-amp with a diode in the forward feedback path and a capacitor from the output node to ground, with a reset switch in parallel with the capacitor to clear the held value.
Function in a circuit
The peak detector captures the maximum voltage of a time-varying input signal. When the input voltage rises above the currently held output voltage, the op-amp drives the diode into forward conduction, charging the hold capacitor to the new peak value. When the input voltage falls below the held level, the op-amp output swings negative, the diode blocks, and the capacitor holds the previous peak voltage at the output. A reset mechanism (switch or transistor across the capacitor) is typically provided to discharge the hold capacitor and reset the output to zero when required. Droop (voltage decay during hold) is minimised by using a high-input-impedance op-amp buffer and a low-leakage capacitor.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617 does not define a specific peak detector symbol; it is represented as a functional block per IEC 60617-02 (symbol elements for block diagrams) with appropriate input/output labels. Operational amplifier symbols within the detailed circuit follow IEC 60617-05 (semiconductor symbols). |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2 / IEEE 315 represents the peak detector as a functional block symbol (rectangle with descriptive label) in system-level and block diagrams. The internal op-amp, diode, and capacitor components are drawn using their respective IEEE 315 symbols in detailed circuit schematics. |
| Key difference | IEC 60617 and ANSI Y32.2/IEEE 315 both represent the peak detector as a labelled rectangular block at the system level. Both standards are identical in this regard; detailed implementation schematics use standard op-amp, diode, and capacitor symbols defined in IEC 60617-05 or IEEE 315. |
Terminals / pins
| Pin | Name |
|---|---|
| in | In |
| out | Out |
Typical values
Input voltage range: ±Vsupply (limited by op-amp supply rails). Hold capacitor: 10 nF–10 µF (droop vs. bandwidth trade-off). Diode forward voltage: 0.2–0.3 V (Schottky) to minimise offset; ideally compensated by op-amp feedback loop. Droop rate: depends on capacitor value and op-amp input bias current (typically < 1 mV/ms for precision types). Response time (rise): determined by op-amp slew rate and diode capacitance. Reset time: < 1 µs with active reset transistor.
Where the Peak Detector symbol is used
- Audio VU and peak metering: capturing and displaying peak signal levels in mixing consoles, DAWs, and broadcast equipment
- Motor drive fault detection: detecting peak current or voltage transients that indicate motor winding faults or overcurrent events
- Ultrasonic distance measurement: holding the peak of the echo pulse from an ultrasonic transducer for ADC conversion
- Power supply output monitoring: detecting peak overvoltage transients on regulated supply outputs for protection triggering
- Vibration and shock monitoring: capturing the peak acceleration value of a transient shock event from an accelerometer output
- RF envelope detection: extracting the amplitude envelope of amplitude-modulated (AM) RF signals in receivers
Example
In an audio peak meter circuit, a peak detector block is connected between the audio signal output (In) and an ADC input (Out): when the audio signal reaches a new peak amplitude, the peak detector charges its hold capacitor to that level within microseconds; the ADC reads the held voltage and displays the peak dBu level on the meter. A reset pulse clears the peak hold at defined intervals (e.g. once per second) to allow new peak captures.
Key facts
- A peak detector captures and holds the maximum (peak) voltage of an input waveform at its output; the basic circuit uses an op-amp, a diode in the forward feedback path, and a hold capacitor.
- The peak detector circuit operates as follows: when input exceeds held output, the op-amp charges the capacitor via the diode to the new peak; when input falls, the diode blocks reverse current and the capacitor retains the peak voltage.
- Schottky diodes (forward voltage 0.2–0.3 V) are preferred over silicon PN diodes (0.6–0.7 V) in precision peak detectors to minimise the output offset, or a second op-amp is used in the diode loop to compensate the forward voltage error.
- Droop — slow decay of the held peak voltage due to capacitor leakage and op-amp input bias current — is minimised by using JFET or CMOS input-stage op-amps (pA-level bias current) and low-leakage polypropylene or film capacitors.
- A reset switch (transistor or analogue switch in parallel with the hold capacitor) is required to clear the held peak and allow capture of a new maximum value; without reset, the circuit holds the highest voltage seen since power-up.
- IEC 60617 and ANSI Y32.2/IEEE 315 represent the peak detector as a labelled rectangular functional block in block diagrams; internal components (op-amp, diode, capacitor) use their respective IEC/IEEE symbols in detailed schematics.
- Common op-amp choices for precision peak detectors include the LM358, LT1078, and AD8032, selected for low input offset voltage, low input bias current, and sufficient slew rate for the input signal bandwidth.
Frequently asked questions
What does the peak detector symbol look like?
The peak detector symbol is a rectangular block labelled 'Peak Detector' or 'PEAK HOLD' with an input terminal (In) on the left and an output terminal (Out) on the right. In detailed schematics, the peak detector circuit is drawn showing an op-amp with a diode in its feedback path and a hold capacitor from the output node to ground. A reset switch in parallel with the capacitor may also be shown.
What does a peak detector circuit do?
A peak detector captures and holds the maximum voltage of an input signal at its output. When the input rises above the currently held value, the circuit charges a capacitor to the new peak. When the input falls, a diode blocks reverse current and the capacitor retains the peak voltage. The output therefore equals the highest voltage the input has reached since the last reset.
What components make up a peak detector circuit?
A basic peak detector consists of three components: an op-amp (typically JFET-input for low bias current), a diode (Schottky preferred for low forward voltage) in the feedback path from the op-amp output to the inverting input, and a hold capacitor from the output node to ground. A reset switch (analogue switch or MOSFET) in parallel with the capacitor allows the held peak to be cleared.
What is the difference between a peak detector and an envelope detector?
A peak detector captures the absolute maximum voltage of a signal and holds it until reset. An envelope detector tracks the varying amplitude envelope of a signal, following peaks and valleys with a time constant set by the RC component values. The envelope detector allows the held value to decay (following the signal amplitude) while the peak detector holds the highest value indefinitely until actively reset.
What standard defines the peak detector symbol?
IEC 60617 and ANSI Y32.2/IEEE 315 both represent the peak detector as a labelled rectangular functional block symbol in system and block diagrams, following the general block diagram conventions of IEC 60617-02 and IEEE 315. There is no dedicated peak detector glyph in either standard; the block is identified by its descriptive text label.
What causes droop in a peak detector and how is it minimised?
Droop is the slow decay of the held peak voltage caused by leakage current discharging the hold capacitor: sources include the op-amp's input bias current, the diode's reverse leakage current, and PCB surface leakage. Droop is minimised by using a JFET or CMOS input-stage op-amp (pA-level input bias current), a Schottky diode with low reverse leakage, a low-leakage polypropylene or film hold capacitor (10 nF–1 µF), and guard rings on the PCB to isolate the hold node.
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