Sample and Hold Symbol
Definition: The Sample and Hold symbol represents an analog circuit that captures (samples) the instantaneous value of an input voltage on command and retains (holds) that voltage at its output until the next sample command, depicted as a rectangular block with an In pin, an Out pin, and an S/H control pin, used in signal-processing and data-acquisition circuit diagrams preceding an analog-to-digital converter to freeze the input during conversion.
Also known as: S/H circuit, track-and-hold, T/H amplifier, sample-hold amplifier, SHA, LF398.
What the Sample and Hold symbol means
The Sample and Hold symbol in a circuit diagram represents a fundamental analog signal-processing block that bridges the continuous analog world and the discrete digital domain. During the sample (track) phase — when the S/H control pin is HIGH — the circuit tracks the input voltage in real time. When the S/H control transitions to the hold command, the circuit freezes the instantaneous input voltage on a capacitor and presents that frozen voltage to the output, where it remains stable until the next sample command.
In data-acquisition and ADC circuit schematics, the sample-and-hold symbol precedes an analog-to-digital converter. Because an ADC requires a finite conversion time during which the input must remain constant, the sample-and-hold circuit freezes the signal, eliminating aperture error caused by input voltage changes during conversion. The sample-and-hold is essential for accurately digitising rapidly changing signals at high sample rates.
How to identify the Sample and Hold symbol
The Sample and Hold symbol is drawn as a rectangle labelled 'S/H' or 'Sample & Hold' with an analog input pin labelled 'In' on the left, an analog output pin labelled 'Out' on the right, and a control pin labelled 'S/H' or 'CTRL' at the bottom. Some symbols include a VCC and GND supply pin. The S/H control input is typically a digital logic signal. The symbol resembles an op-amp or buffer block but is specifically identified by the S/H control pin and the S&H or T/H label.
Function in a circuit
A sample-and-hold circuit operates in two phases. In the track (sample) phase, an analog switch (FET) connects the input signal to a hold capacitor through a buffer amplifier, and the capacitor charges to track the input voltage. When the S/H control pin transitions to hold, the analog switch opens, disconnecting the input. The capacitor retains the last sampled voltage, and an output buffer amplifier with high input impedance presents the frozen voltage to the output with negligible droop. The circuit then remains in hold until the next sample command, providing a stable, settled input to the ADC during its conversion cycle.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617 does not define a dedicated symbol for sample-and-hold circuits. IEC practice uses a functional block rectangle labelled 'S/H' or 'T/H' with labelled signal pins per IEC 60617-12. |
|---|---|
| ANSI/IEEE 315 | ANSI/IEEE 315 does not specify a sample-and-hold symbol. The circuit is represented as a rectangular functional block with In, Out, and CTRL pin labels per IEEE 315 IC symbol conventions. The LF398 datasheet (Texas Instruments) shows the industry-standard block representation. |
| Key difference | No IEC vs ANSI standard symbol difference exists. Both use a rectangular functional block. The label 'S/H' (sample-hold) or 'T/H' (track-hold) and the pin designations In, Out, S/H (or CTRL) are de-facto conventions established by IC manufacturer datasheets. |
Terminals / pins
| Pin | Name |
|---|---|
| in | In |
| out | Out |
| ctrl | S/H |
Typical values
Acquisition time: 4–10 µs typical (LF398). Aperture time: 150–3000 ps (device dependent). Hold droop rate: 5 mV/ms typical (capacitor + FET leakage dependent). Hold capacitor: 0.01–10 µF (external, user-selected). Input voltage range: ±10 V typical. Bandwidth (track mode): DC to several MHz. Power supply: ±5 V to ±15 V.
Where the Sample and Hold symbol is used
- Preceding successive approximation ADCs (SAR ADCs) in data-acquisition systems to freeze the input signal during the multi-clock conversion cycle
- Multiplexed multi-channel ADC systems where one S/H per channel holds its sample while a shared ADC sequentially converts each channel
- Phase-locked loop (PLL) analog front ends for holding a sampled phase-error voltage between PLL corrections
- Peak detectors in radar and ultrasonic ranging systems that freeze the peak envelope of a pulse
- Digital oscilloscope front-end sampling chains where the input is sampled at a precise aperture time
- Motor control current-sense circuits where the phase current sample is held during the PWM dead-time for accurate ADC conversion
Example
In a 12-bit SAR ADC data-acquisition card, the Sample and Hold symbol shows the In pin receiving an analog sensor signal (0–5 V), the Out pin connected to the AIN pin of an MCP3208 SAR ADC, and the S/H control pin driven by the microcontroller; the microcontroller asserts S/H LOW (hold) before initiating the ADC conversion, freezing the sensor voltage on the 100 pF internal hold capacitor for the 1.5 µs conversion time, then releases S/H HIGH (track) to acquire the next sample.
Key facts
- Aperture time is the uncertainty in the precise moment the input is disconnected from the hold capacitor; a shorter aperture time reduces aperture error when sampling high-frequency signals (aperture error = dV/dt × aperture time).
- Hold droop is the slow decay of the held voltage due to leakage current through the analog switch FET and hold capacitor dielectric; a larger hold capacitor reduces droop rate at the cost of longer acquisition time.
- Acquisition time is the time required for the hold capacitor to charge to within a specified accuracy (e.g., 0.01%) of the new input value after transitioning from hold to track mode; it must be less than the time between samples.
- The LF398 (Texas Instruments) and LF198 are classic sample-and-hold ICs with an internal op-amp, FET switch, and logic input; they require an external hold capacitor (0.01–10 µF) to set acquisition time and droop rate.
- In modern ADC ICs, the sample-and-hold function is integrated on-chip ahead of the conversion logic, so the S/H block does not always appear as a separate symbol in contemporary circuit diagrams.
- The S/H circuit introduces a zero-order hold (ZOH) transfer function in the sampled-data signal path, which has a frequency-domain sinc(f) roll-off that must be compensated in precision measurement systems.
- Track-and-hold (T/H) is a synonym for sample-and-hold emphasising that the circuit continuously tracks the input in one phase, in contrast to a pure S/H that only connects to the input briefly during the sample pulse.
Frequently asked questions
What does the sample and hold symbol mean in a circuit diagram?
The sample and hold symbol represents an analog circuit that freezes the instantaneous value of the input voltage on a hold capacitor when the S/H control pin commands 'hold', and tracks the input again when commanded 'sample'. It is used ahead of ADCs to keep the input stable during the conversion period.
What does a sample-and-hold circuit symbol look like?
The sample-and-hold symbol is a rectangle labelled 'S/H' or 'Sample & Hold' with an 'In' pin on the left, an 'Out' pin on the right, and an 'S/H' or 'CTRL' control pin at the bottom. Supply pins (VCC, GND) may be included. The block is similar to an op-amp or buffer but is identified by the S/H control pin.
Why is a sample-and-hold circuit used before an ADC?
An ADC requires the input voltage to remain stable during its conversion time (typically 1–10 µs). Without a sample-and-hold, a fast-changing input signal would change value during conversion, causing aperture error in the digital output. The sample-and-hold freezes the input at a precise moment, eliminating this error.
What is aperture time in a sample-and-hold circuit?
Aperture time is the delay and uncertainty between the hold command and the moment the analog switch fully opens, disconnecting the input from the hold capacitor. Aperture error equals the input slew rate (dV/dt) multiplied by the aperture time uncertainty; a 1 ps aperture time allows sampling a 1 V/ns signal with negligible error.
What is hold droop in a sample-and-hold circuit?
Hold droop is the gradual decay of the held voltage due to leakage current flowing through the analog switch FET and the hold capacitor dielectric. Droop is typically 1–10 mV/ms and is reduced by using a larger hold capacitor or a lower-leakage capacitor type (polypropylene or C0G ceramic).
What is the difference between sample-and-hold and track-and-hold?
Track-and-hold (T/H) continuously follows (tracks) the input during the track phase, whereas a pure sample-and-hold briefly connects to the input for a very short aperture pulse and then disconnects. Modern ICs use track-and-hold architecture for lower noise; the terms are used interchangeably in most datasheets and circuit diagrams.
What IC is commonly used for a sample-and-hold circuit?
The LF398 (Texas Instruments, National Semiconductor) and LF198 are classic dedicated sample-and-hold ICs with an internal op-amp, FET switch, and logic-level compatible control input requiring an external hold capacitor. Modern data-acquisition systems typically use ADCs with integrated S/H (e.g., ADS8685, MCP3208) that do not require an external S/H IC.
Place the Sample and Hold symbol on a wiring diagram or schematic in the free online circuit diagram maker — no download required.