BCD Counter Symbol
Definition: The BCD Counter symbol represents a digital integrated circuit that counts input clock pulses and outputs the count in 4-bit Binary Coded Decimal (BCD) format, cycling from 0000 (decimal 0) through 1001 (decimal 9) before resetting, as defined in IEEE 91-1984 / IEC 60617-12 logic symbol conventions.
Also known as: decade counter, mod-10 counter, BCD decade counter, 7490 counter, 4-bit BCD counter.
What the BCD Counter symbol means
The BCD Counter symbol denotes a synchronous or asynchronous counter IC that produces a four-bit output (QA, QB, QC, QD) representing decimal digits 0–9 in 8-4-2-1 weighted BCD code. Each rising (or falling) edge of the clock input increments the count by one; after reaching 1001 (decimal 9) the counter resets to 0000 on the next clock pulse.
BCD counters are fundamental building blocks in digital systems that must interface with decimal display hardware such as 7-segment displays. The 74-series TTL device 7490 and the CMOS 4518 are classic BCD counter ICs. The symbol appears in logic diagrams to show clock source, reset control, and 4-bit BCD output bus connections.
How to identify the BCD Counter symbol
The BCD Counter symbol is drawn as a rectangular logic block with a clock input (CLK) and reset input (RST) on the left side, four output lines (QA, QB, QC, QD) on the right side representing bits 0–3 of the BCD count, and power supply pins (VCC at top, GND at bottom). A modulus annotation 'MOD-10' or 'BCD' is typically written inside or adjacent to the rectangle to distinguish it from binary counters.
Function in a circuit
A BCD counter IC counts from 0 to 9 in binary coded decimal on each clock edge, providing four parallel output lines QA (LSB, weight 1), QB (weight 2), QC (weight 4), and QD (MSB, weight 8). A reset (RST) input forces all outputs to 0000 synchronously or asynchronously. Multiple BCD counters are cascaded — the carry or ripple output of one counter clocking the next — to count into the tens, hundreds, and higher decimal digits.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 defines rectangular-block logic symbols for combinational and sequential functions. A BCD counter is shown as a rectangle with 'CTR DIV 10' (counter, divide-by-10) as the qualifying symbol inside the block, with dependency notation for clock and reset inputs per IEC 60617-12. |
|---|---|
| ANSI/IEEE 315 | IEEE 91-1984 (ANSI Y32.14) specifies the same rectangular-block logic symbol convention with 'CTR DIV 10' inside. Input and output labels follow IEEE 91 dependency notation (C for clock, R for reset, Q for output). |
| Key difference | IEC 60617-12 and IEEE 91-1984 use identical rectangular-block notation for BCD counters; differences appear only in pin-label dependency notation conventions, not in the fundamental block shape. |
Terminals / pins
| Pin | Name |
|---|---|
| clk | CLK |
| rst | RST |
| qa | QA |
| qb | QB |
| qc | QC |
| qd | QD |
| vcc | VCC |
| gnd | GND |
Typical values
Clock frequency: DC to 35 MHz (7490 TTL) or up to 6 MHz (4518 CMOS at 5 V). Supply voltage: 4.75–5.25 V (TTL), 3–15 V (CMOS). Output drive: standard TTL 8 mA sink / 400 µA source; CMOS varies with VCC.
Where the BCD Counter symbol is used
- Digital clocks and timers where seconds and minutes must be displayed in decimal on 7-segment displays
- Frequency dividers that divide an input clock by 10 to step down frequency by one decade
- Event counters in industrial automation panels counting parts, pulses, or operations per cycle
- Cascade counter chains (units, tens, hundreds) for multi-digit decimal counting in scoreboard and tally systems
- BCD-to-7-segment decoder driver circuits (e.g. 7490 + 7447 combination) in educational electronics kits
- Digital meters and measurement instruments requiring decimal readout of analog-to-digital converted values
Example
In a simple digital clock seconds display, two BCD Counter symbols are shown cascading: the first counter's CLK pin connects to a 1 Hz clock source; its QA–QD outputs feed a 7447 BCD-to-7-segment decoder driving the units digit display. When the first counter's carry output pulses the second counter's CLK pin, the tens digit increments, and a reset decoder forces both counters to 0000 when the tens digit reaches 6, yielding a 0–59 seconds count.
Key facts
- A BCD counter counts from decimal 0 (binary 0000) to decimal 9 (binary 1001) and resets on the next clock pulse, making it a modulo-10 (MOD-10) counter.
- Outputs are QA (bit 0, weight 1), QB (bit 1, weight 2), QC (bit 2, weight 4), QD (bit 3, weight 8) — the 8-4-2-1 BCD weighting.
- The IEC 60617-12 / IEEE 91-1984 symbol notation for a BCD counter uses 'CTR DIV 10' inside a rectangular logic block.
- Classic BCD counter ICs include the TTL 7490 (asynchronous) and CMOS 4518 (synchronous dual BCD counter).
- BCD counter chains are cascaded so that each carry/ripple output clocks the next higher-order counter to count into decimal tens, hundreds, etc.
- The reset pin (RST or CLR) forces all outputs to 0000 and is used to restart counts or truncate counting sequences shorter than 9.
- BCD output is incompatible with straight binary counting — the binary states 1010 through 1111 (10–15) are invalid BCD states and are skipped.
- Pins: CLK (clock input), RST (reset), QA, QB, QC, QD (BCD outputs), VCC (+5 V supply), GND (ground).
Frequently asked questions
What does the BCD counter symbol mean in a logic diagram?
The BCD counter symbol represents a decade counter IC that counts from 0 to 9 in 4-bit Binary Coded Decimal format. Each clock pulse advances the count by one; after 9 the counter resets to 0. The four outputs QA–QD carry the 8-4-2-1 weighted bits of the current decimal count.
What does a BCD counter symbol look like?
The BCD counter symbol is a rectangle with 'CTR DIV 10' or 'BCD' written inside, clock (CLK) and reset (RST) inputs on the left, four outputs QA–QD on the right, and VCC/GND supply pins at top and bottom. This notation follows IEC 60617-12 and IEEE 91-1984 rectangular logic-block conventions.
What is the difference between a BCD counter and a binary counter?
A BCD counter counts from 0 to 9 (modulo-10) and produces outputs in 8-4-2-1 weighted decimal format, skipping binary states 10–15. A binary counter counts from 0 to 15 (modulo-16) using all four-bit combinations. BCD counters interface directly with decimal displays; binary counters are used in address decoding and arithmetic circuits.
What is the IEC symbol notation for a BCD counter?
Under IEC 60617-12 and IEEE 91-1984, a BCD counter is represented as a rectangular block with the qualifying symbol 'CTR DIV 10' inside. Inputs use dependency notation: C for clock, R for reset. Outputs are labelled Q with positional suffixes. This notation is identical in both IEC and ANSI/IEEE standards.
How do you cascade BCD counters for multi-digit counting?
Connect the carry or ripple-carry output (or QD of the units counter combined with a NAND gate) to the CLK input of the next counter. The second counter then represents the tens digit, the third the hundreds digit, and so on. Each counter independently cycles 0–9 in BCD, enabling arbitrarily long decimal count chains.
What are the pin names on a BCD counter symbol?
Standard BCD counter pins are CLK (clock input), RST or CLR (reset/clear), QA (bit 0, weight 1), QB (bit 1, weight 2), QC (bit 2, weight 4), QD (bit 3, weight 8), VCC (positive supply, typically +5 V), and GND (ground). Some devices add enable (EN) or carry-out (CO) pins.
What common ICs implement a BCD counter?
The TTL 7490 is the classic asynchronous BCD decade counter. The CMOS 4518 contains two synchronous BCD counters in one package. The 74HC390 provides two independent decade counters in a single SOIC package, and the 74HC4017 is a Johnson decade counter used for sequencing applications.
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