Frequency Divider Symbol
Definition: The Frequency Divider symbol represents a digital circuit block that outputs a clock signal whose frequency is an integer fraction (1/N) of the input clock frequency, shown in block diagrams as a rectangle labelled '÷N' or 'Frequency Divider' with a CLK In (clk_in) input, a divisor control input N (n), and a CLK Out (clk_out) output.
Also known as: clock divider, prescaler, divide-by-N counter, frequency prescaler, digital divider, counter-divider.
What the Frequency Divider symbol means
The Frequency Divider symbol denotes a synchronous digital circuit, commonly implemented as a binary counter or programmable counter, that produces one output clock pulse for every N input clock pulses. The division ratio N is set either by hardwiring (for fixed division) or by a programmable input (N pin), allowing dynamic control of the output frequency.
The three terminals — CLK In (clk_in) for the input clock signal, N (n) for the programmable division ratio, and CLK Out (clk_out) for the divided output — appear in phase-locked loop (PLL) system diagrams, clock distribution networks, and digital timing circuits. Frequency dividers are fundamental building blocks in synthesisers, microcontroller clock systems, and communication PLLs.
How to identify the Frequency Divider symbol
The frequency divider symbol is drawn as a rectangular block labelled 'Freq Div', '÷N', or 'Frequency Divider'. The CLK In (clk_in) pin enters from the left side and carries the high-frequency reference clock. The N (n) pin, also on the left side, accepts the binary or BCD division ratio from a register or hardwired logic. The CLK Out (clk_out) pin exits from the right side and delivers the divided clock. A clock edge arrow (>) may mark the CLK In pin to indicate edge-triggered operation.
Function in a circuit
A frequency divider works by counting input clock edges and toggling the output after every N counts. For a divide-by-2, the output flips state on every rising edge of the input, producing a square wave at exactly half the input frequency with a 50% duty cycle. For divide-by-N (N > 2), a counter increments on each input edge and generates an output pulse or toggles when the count reaches N, then resets. Programmable dividers accept a digital word on the N input to set the division ratio dynamically, enabling frequency synthesis when placed inside a PLL feedback path.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 defines binary counter and divider symbols for logic diagrams; the frequency divider is represented as a rectangular function block with qualifying input and output labels per IEC 60617 logic symbol conventions. |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2 / IEEE 315-1975 and IEEE Std 91 (Logic Symbols for Digital Devices) define counter and divider block symbols with dependency notation. The frequency divider is typically shown as a CTR (counter) block with a division-ratio annotation or as a ÷N block. |
| Key difference | IEC 60617-12 uses a qualifying label inside the rectangle (e.g., 'DIV N' or '÷N') with standardised pin notation. IEEE 91 (used in North American practice) uses the CTR block with appropriate mode inputs annotated. Both show three key connections: clock input, control/ratio input, and clock output. |
Terminals / pins
| Pin | Name |
|---|---|
| clk_in | CLK In |
| n | N |
| clk_out | CLK Out |
Typical values
Division ratio N: 2 to 2^32 (software-programmable PLLs); maximum input frequency: up to 10 GHz for RF prescalers (e.g., HMC361); power supply: 1.8 V or 3.3 V for CMOS logic; output duty cycle: 50% for power-of-2 dividers; phase noise: typically 20·log(N) dB degradation from input to output.
Where the Frequency Divider symbol is used
- PLL feedback dividers: the divide-by-N block in a phase-locked loop sets the output frequency as a multiple of the reference frequency (fout = N × fref)
- Microcontroller clock prescalers: the CPU clock is divided down from the oscillator frequency to set peripheral timer tick rates
- RF frequency synthesisers: fractional-N dividers enable fine frequency steps in VHF/UHF synthesisers for radio receivers and transmitters
- UART baud rate generation: a baud rate generator divides the system clock to produce the required bit-period timing
- ADC sample clock derivation: a fixed divider produces an ADC sample clock from a higher-frequency master clock
- Digital frequency counter circuits: a chain of divide-by-10 stages scales a high-frequency input down to a range measurable by a gate counter
Example
In a 100 MHz PLL clock multiplier, the feedback path contains a frequency divider block with CLK In (clk_in) connected to the VCO output running at 2.4 GHz, N (n) set to 24 by a control register, and CLK Out (clk_out) returning a 100 MHz divided signal to the phase detector. The PLL phase detector compares this 100 MHz feedback clock to a 100 MHz crystal reference and adjusts the VCO until both are phase-locked, producing a clean 2.4 GHz output from a 100 MHz reference.
Key facts
- The Frequency Divider symbol represents a digital counter block that outputs one clock pulse for every N input clock pulses, reducing frequency by a factor of N.
- The three terminals are CLK In (clk_in) for the reference input clock, N (n) for the programmable division ratio, and CLK Out (clk_out) for the frequency-divided output.
- A divide-by-2 frequency divider produces a perfect 50% duty cycle output at exactly half the input frequency; higher integer dividers may produce asymmetric duty cycles unless specially designed.
- In a phase-locked loop (PLL), the frequency divider in the feedback path sets the output frequency as fout = N × fref, where fref is the reference input to the phase detector.
- Phase noise degrades by 20·log10(N) dB through a divide-by-N stage, so large division ratios increase output phase noise relative to the input.
- Fractional-N dividers achieve non-integer division ratios by rapidly switching between N and N+1 using a sigma-delta modulator, enabling fine frequency steps in RF synthesisers.
- Maximum input frequency for CMOS logic dividers is typically 500 MHz to 2 GHz; RF prescaler ICs (e.g., bipolar HBT) divide frequencies up to 10 GHz or beyond.
Frequently asked questions
What does the frequency divider symbol mean in a circuit diagram?
The frequency divider symbol represents a digital block that reduces a clock signal's frequency by a programmable integer factor N, outputting one pulse for every N input pulses. It appears in PLL, synthesiser, and clock distribution circuit diagrams.
What does the frequency divider symbol look like?
The frequency divider symbol looks like a rectangular block labelled '÷N' or 'Frequency Divider'. CLK In (clk_in) enters from the left, N (n) — the division ratio control — also enters from the left, and CLK Out (clk_out) exits from the right. A clock edge marker (>) may annotate the CLK In pin.
How does a frequency divider work?
A frequency divider works by counting incoming clock edges. After N edges, it produces one output pulse (or toggles the output once), then resets the count. For divide-by-2, a single D flip-flop with Q fed back to D inverted accomplishes this; for larger N, a counter with a comparator or decode logic is used.
What is the difference between a prescaler and a frequency divider?
A prescaler is a type of frequency divider, typically used at the input of a synthesiser PLL to divide a very high (RF) frequency down to a range the main programmable counter can handle. Prescalers are usually fixed-ratio (e.g., ÷8 or ÷64) or dual-modulus (e.g., ÷8/9), while programmable dividers accept an N-bit word to set any ratio.
What is the standard that defines the frequency divider symbol?
The frequency divider symbol is defined by IEC 60617-12 for digital function blocks in logic diagrams and by IEEE Std 91 (Logic Symbols for Digital Devices) in North American practice. Both represent it as a rectangular block with labelled clock and control inputs.
What happens to phase noise when a signal passes through a frequency divider?
Passing a signal through a divide-by-N frequency divider reduces phase noise by 20·log10(N) dB. This is why high-quality frequency references are often multiplied up from a low-frequency crystal oscillator using a PLL; the crystal's excellent close-in phase noise is preserved and frequency-multiplied noise is tolerable.
What is a fractional-N frequency divider?
A fractional-N frequency divider achieves non-integer division ratios (e.g., ÷23.5) by rapidly alternating between divide-by-N and divide-by-(N+1) using a sigma-delta modulator to control the switching pattern. This enables fine frequency resolution in PLL synthesisers without requiring very high reference frequencies.
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