JK Flip-Flop Symbol
Definition: The JK Flip-Flop symbol represents a clocked bistable sequential logic element in circuit diagrams, drawn as a rectangular block with inputs J, CLK, and K on the left and outputs Q and Q̅ (Q-bar) on the right, standardised under IEC 60617-12 and ANSI Y32.14 / IEEE 91-1984, used in digital circuits for toggling, counting, frequency division, and shift-register operations.
Also known as: JKFF, JK bistable, JK master-slave flip-flop, JK latch (informal), toggle flip-flop.
What the JK Flip-Flop symbol means
The JK Flip-Flop symbol denotes a synchronous bistable storage element that samples its J and K inputs on the active clock edge and changes state according to the JK truth table: J=0,K=0 holds state; J=1,K=0 sets Q to 1; J=0,K=1 resets Q to 0; J=1,K=1 toggles Q to the opposite state. The Q̅ output is always the logical complement of Q.
In digital logic diagrams, the JK flip-flop is a fundamental building block for counters, frequency dividers, and state machines. Unlike the SR flip-flop, the J=1,K=1 condition is valid and causes toggling rather than an undefined state, making the JK the most general-purpose edge-triggered bistable. The clock (CLK) input synchronises all state transitions to a common timing reference.
How to identify the JK Flip-Flop symbol
The JK Flip-Flop symbol is a rectangle with five labelled connection points: J and K on the upper and lower left for the data inputs, CLK (or a small triangle on the left edge) in the middle for the clock input, Q on the upper right for the true output, and Q̅ (a Q with an overbar, or Qn) on the lower right for the complementary output. The clock triangle symbol indicates edge-triggering; a bubble (small circle) before the triangle denotes negative-edge (falling-edge) triggering. Optional preset (PRE) and clear (CLR) pins may appear on the top and bottom.
Function and usage boundary
The JK Flip-Flop captures the state of inputs J and K at each active clock edge and updates its stored bit accordingly: set (J=1,K=0), reset (J=0,K=1), hold (J=0,K=0), or toggle (J=1,K=1). The Q output represents the stored bit; Q̅ is its complement. By connecting Q̅ back to both J and K inputs, the flip-flop always sees J=1,K=1 and toggles on every clock edge, dividing the clock frequency by two — the basis of binary ripple counters.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 (binary logic elements): the JK flip-flop is represented as a rectangular block with the function identifier 'JK' inside, edge-trigger symbol (triangle) on the CLK input, and output pins Q and Q̅. Negated outputs are shown with a small circle (bubble) at the pin. |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.14-1973 / IEEE 91-1984 (logic symbols for digital circuits): uses the same rectangular block convention with 'JK' label, triangle for edge-triggered clock, and Q/Q̅ outputs. The IEEE 91 'distinctive shape' style uses the same rectangular block for flip-flops. |
| Key difference | IEC 60617-12 and ANSI Y32.14 / IEEE 91-1984 are functionally identical for the JK flip-flop symbol: both use a rectangle labeled 'JK' with a clock triangle and Q/Q̅ output pins. Minor differences in pin label fonts and placement convention exist between software tools but not in the standards themselves. |
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Logical terminals
| Logical ID | Editor terminal name |
|---|---|
| j | J |
| clk | CLK |
| k | K |
| q | Q |
| qn | Q̅ |
Where the JK Flip-Flop symbol is used
- Binary ripple counters and synchronous counters in frequency dividers and clock generation circuits
- Shift registers and serial-to-parallel data converters in digital communication interfaces
- State machine implementations in digital controllers and sequencers
- Frequency division by two (T flip-flop mode with Q̅ fed back to J and K inputs)
- Synchronising asynchronous input signals to a system clock (metastability reduction with two flip-flops in series)
- PWM waveform generation and duty-cycle halving in motor control and power electronics
Key facts
- The JK Flip-Flop symbol is an IEC 60617-12 / ANSI Y32.14 rectangular block labeled 'JK' with inputs J (top-left), CLK (middle-left, shown with an edge-trigger triangle), K (bottom-left), and outputs Q (top-right) and Q̅ (bottom-right).
- The four JK input combinations define unique behaviours: J=0,K=0 (hold), J=1,K=0 (set Q=1), J=0,K=1 (reset Q=0), J=1,K=1 (toggle Q to opposite state).
- With J=1,K=1 (both high), the flip-flop toggles on every active clock edge, acting as a T (toggle) flip-flop that divides the clock frequency by two.
- The JK flip-flop resolves the undefined state of the SR flip-flop: J=1,K=1 is a valid and defined condition (toggle), making the JK the most versatile general-purpose bistable.
- Setup time is the minimum period J and K must be stable before the active clock edge; violating it risks metastability where Q settles to an indeterminate voltage.
- Common ICs: 74HC73 (dual JK, negative-edge), 74HC112 (dual JK with preset/clear, negative-edge), CD4027 (CMOS, positive-edge).
- The designator for a flip-flop IC in a schematic is U (or IC) per IEC 60617 and ANSI Y32.2 / IEEE 315, e.g., U3.
Frequently asked questions
What does the JK Flip-Flop symbol mean in a circuit diagram?
The JK Flip-Flop symbol represents a clocked bistable that samples inputs J and K on the active clock edge and updates its stored bit: J=1,K=0 sets Q to 1; J=0,K=1 resets Q to 0; J=0,K=0 holds; J=1,K=1 toggles Q. It is used wherever a synchronous 1-bit memory element with set, reset, hold, or toggle capability is needed.
What does the JK Flip-Flop symbol look like?
The JK Flip-Flop symbol is a rectangle with the letter labels J (upper-left input), CLK (middle-left, with a small triangle indicating edge-triggering), and K (lower-left input) on the left side, and Q (upper-right) and Q̅ (lower-right, Q with an overbar) on the right side. A bubble on the CLK triangle indicates falling-edge triggering.
What is the difference between a JK flip-flop and a D flip-flop?
A D flip-flop has a single data input D and simply copies D to Q on the active clock edge (no toggle mode). A JK flip-flop has two inputs J and K enabling four distinct behaviours including toggling when both are high. D flip-flops are simpler and preferred for data registers; JK flip-flops are used when toggle or independent set/reset capability is needed.
What does J=1, K=1 mean for a JK flip-flop?
When both J and K are logic high (J=1, K=1), the JK flip-flop toggles on each active clock edge: if Q was 0 it becomes 1, if Q was 1 it becomes 0. This is the toggle (T) mode and is the defining feature that distinguishes the JK from the SR flip-flop, where S=1, R=1 is a forbidden (undefined) condition.
What standard defines the JK flip-flop symbol?
The JK flip-flop symbol is standardised in IEC 60617-12 (binary logic elements) for IEC schematics, and in ANSI Y32.14-1973 / IEEE 91-1984 (logic symbols for digital circuits) for North American schematics. Both standards use a rectangular block labeled 'JK' with an edge-trigger indicator on the clock input.
How is a JK flip-flop used as a frequency divider?
To create a divide-by-two circuit, connect both J and K inputs to logic high (Vcc). The flip-flop is permanently in toggle mode and switches Q on every active clock edge, producing an output at half the clock frequency. Cascading multiple flip-flops in this configuration creates a binary ripple counter where each stage halves the previous frequency.
What is the designator letter for a JK flip-flop in a schematic?
When a JK flip-flop is a standalone IC or part of an integrated circuit, the reference designator is U (or IC) per IEC 60617 and ANSI Y32.2 / IEEE 315, e.g., U1, U2. If drawn as a logic symbol within a larger digital schematic, individual element designators such as FF1, FF2 are sometimes used informally.
Related symbols
- 4-Bit Counter symbol
- BCD Counter symbol
- D Flip-Flop symbol
- Switch (3-Way) symbol
- Switch (SPST) symbol
- T Flip-Flop symbol
Physical breadboard, PCB, and panel mapping
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