Decoder (3:8) Symbol
Definition: The Decoder (3:8) symbol represents a combinational logic functional block that decodes a 3-bit binary input address into one of eight unique active output lines, activating exactly one output at a time corresponding to the binary value of the address inputs, implemented by devices such as the 74HC138 and defined as a functional block per IEEE Std 91-1984 / IEC 60617-12.
Also known as: 3-to-8 decoder, 3:8 decoder, binary decoder, one-of-eight decoder, 74HC138, demultiplexer decoder.
What the Decoder (3:8) symbol means
The Decoder (3:8) symbol denotes a digital logic block that translates a 3-bit binary address (A0, A1, A2) into exactly one of eight output lines (Y0–Y7) asserted high (or low, for active-low outputs). For example, when A2:A0 = 011 (binary 3), output Y3 is activated and all others remain de-asserted. This one-hot output encoding is fundamental in address decoding for memory systems and I/O selection.
In circuit diagrams the decoder block symbol represents a demultiplexing or address-selection function. It is commonly used in microprocessor systems to select one of several peripheral chips based on address bus bits, in display drivers selecting digit positions on multiplexed 7-segment displays, and in logic circuits requiring exclusive selection among multiple outputs.
How to identify the Decoder (3:8) symbol
The Decoder (3:8) symbol is a labelled rectangle inscribed 'DEC 3:8' or 'Decoder (3:8)'. On the left side are three address inputs: A0, A1, and A2 (the 3-bit binary input). On the right side are eight outputs: Y0 through Y7. Enable inputs (often active-low, labelled G̅1, G̅2A, G̅2B on the 74HC138) appear on the left side as additional pins. The symbol may show a bubble on output pins to indicate active-low outputs (ȳ0–ȳ7). The DX:Y notation (3:8) in the label indicates the number of input address bits : number of output lines.
Function in a circuit
A 3:8 binary decoder converts a 3-bit binary address to a one-hot encoded 8-bit output word. For each of the 8 possible address values (000–111), exactly one of the 8 outputs is asserted; all others are de-asserted. Enable inputs allow multiple decoders to be cascaded for larger address spaces (e.g. two 3:8 decoders plus one address bit create a 4:16 decoder). Active-low outputs (as in the 74HC138) are asserted LOW and are suitable for active-low chip-select inputs on memory ICs.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 (Binary Logic Elements) represents the decoder as a labelled rectangular block with 'X/Y DEC' notation indicating the decoding function. The standard defines the general block symbol for combinational logic elements. |
|---|---|
| ANSI/IEEE 315 | IEEE Std 91-1984 / ANSI Y32.14 uses the same rectangular functional block for decoders, with the input-to-output ratio notation. The 74HC138 follows the IEEE 91 symbol convention in most ECAD libraries. |
| Key difference | IEC 60617-12 and IEEE 91 use virtually identical labelled rectangular blocks for the decoder. The notation style may differ slightly (IEC may use 'BIN/OCT DEC'; IEEE 91 may use 'DEC 3/8') but the block shape is the same in both standards. |
Terminals / pins
| Pin | Name |
|---|---|
| a0 | A0 |
| a1 | A1 |
| a2 | A2 |
| y0 | Y0 |
| y1 | Y1 |
| y2 | Y2 |
| y3 | Y3 |
Typical values
Address inputs: 3 (A0, A1, A2). Outputs: 8 (Y0–Y7), active-low on 74HC138. Enable inputs: 3 on 74HC138 (G1 active-high, G̅2A and G̅2B active-low). Supply voltage: 2–6 V (74HC138). Propagation delay: 7–15 ns at 5 V. Fan-out: 10 LS-TTL loads. ICs: 74HC138, 74LS138, 74F138, CD74HCT138.
Where the Decoder (3:8) symbol is used
- Memory address decoding in 8-bit and 16-bit microprocessor systems selecting one of eight ROM or RAM chips.
- Multiplexed 7-segment display digit selection where each decoder output enables one digit's common anode or cathode.
- I/O port address decoding in embedded systems, asserting one peripheral chip-select per address range.
- Priority encoder output decoding converting encoded binary back to one-hot position signals.
- Control logic for data bus arbitration in multi-master systems.
- FPGA I/O expansion circuits selecting one of multiple peripheral devices on a shared data bus.
- Keyboard matrix scanning row/column select drivers for mechanical key switch matrices.
Example
In a Z80 microprocessor system with eight peripheral ICs, the upper three address lines (A13, A14, A15) connect to the A0, A1, A2 inputs of a 74HC138 decoder. Each decoder output (Y0–Y7, active-low) connects to the /CS (active-low chip-select) pin of one peripheral. When the CPU addresses the range 0xE000–0xDFFF, A15:A13 = 101, asserting only Ȳ5 LOW to enable the serial UART IC while all other peripherals remain deselected.
Key facts
- A 3:8 Decoder converts a 3-bit binary address input (A0, A1, A2) to a one-hot 8-bit output, asserting exactly one of eight outputs (Y0–Y7) for each of the 256 possible input combinations.
- The 74HC138 is the standard 3:8 decoder IC; its outputs are active-low (asserted LOW), and it includes three enable inputs (G1, G̅2A, G̅2B) that allow enable-controlled operation and cascading.
- A decoder's outputs are mutually exclusive—only one output is active at any given time—making decoders ideal for chip-select and address-bus demultiplexing applications.
- Two 3:8 decoders can be combined using one additional address bit as the enable selector to form a 4:16 decoder, doubling the addressable outputs.
- IEC 60617-12 and IEEE Std 91-1984 / ANSI Y32.14 both represent the decoder as a labelled rectangular functional block; the standard notation is 'DEC' with input and output bit counts.
- The 7 symbol pins shown in the schematic are: A0, A1, A2 (address inputs), and Y0–Y6 (a representative subset of the eight decoded outputs; full implementations show Y0–Y7).
- A decoder can also function as a DEMUX (demultiplexer) when one of the enable inputs is used as the data input, routing it to the selected output line.
Frequently asked questions
What does the decoder block symbol look like?
The Decoder (3:8) block symbol is a labelled rectangle inscribed 'DEC 3:8' or 'Decoder'. On the left are three address inputs (A0, A1, A2) and enable inputs. On the right are eight outputs (Y0–Y7), often with bubbles indicating active-low logic. The DX:Y ratio label distinguishes it from a multiplexer or other logic blocks.
What does a 3:8 decoder do?
A 3:8 decoder takes a 3-bit binary address input and asserts exactly one of eight output lines that corresponds to the binary value. For example, input 011 (decimal 3) asserts output Y3. The remaining seven outputs are de-asserted, making the outputs mutually exclusive.
What is the difference between a decoder and a demultiplexer?
A decoder converts a binary address to a one-hot output, always activating the selected line as a logic high (or low for active-low types). A demultiplexer routes a single data input to one of several outputs selected by an address. A 74HC138-type decoder can act as a DEMUX by using one of its enable inputs as the data signal, making the two functions closely related.
What are the pins on a 74HC138 3:8 decoder?
The 74HC138 has 16 pins: A0, A1, A2 (3-bit binary address inputs), G1 (active-high enable), G̅2A and G̅2B (active-low enables), Y0–Y7 (eight active-low decoded outputs), VCC, and GND. All three enable inputs must be satisfied (G1=1, G̅2A=0, G̅2B=0) for any output to be active.
How do I build a 4:16 decoder from two 74HC138 chips?
Connect the A0, A1, A2 inputs of both chips in parallel. Use a fourth address bit (A3) to drive G1 of the first chip and G̅2A of the second chip. When A3=0, only the first chip's outputs (Y0–Y7) are active; when A3=1, only the second chip's outputs (Y8–Y15) are active, creating a complete 4:16 decoder.
What standard defines the decoder block symbol?
The decoder is defined as a functional block per IEEE Std 91-1984 (ANSI Y32.14) and IEC 60617-12. Both standards use a labelled rectangle with address inputs on the left and decoded outputs on the right. The 74HC138 device standard is defined by the 74-series logic family specifications (Texas Instruments, NXP).
Why are the outputs of the 74HC138 decoder active-low?
Active-low outputs make the 74HC138 directly compatible with the active-low chip-select inputs (/CS or /CE) found on SRAM, ROM, and peripheral ICs. An active-low output asserts a logic LOW to enable the selected device, matching the LOW-true chip-select convention used throughout TTL and CMOS peripheral ICs.
Place the Decoder (3:8) symbol on a wiring diagram or schematic in the free online circuit diagram maker — no download required.