OR Gate Symbol
Definition: The OR Gate symbol represents a digital logic gate — standardised in IEC 60617-12 and ANSI Y32.2/IEEE 315 — whose output is logic HIGH (1) whenever one or more of its inputs (A or B) are HIGH, implementing the Boolean OR function (Y = A + B); it is drawn as a curved shield shape in ANSI and as a rectangle with the qualifying symbol '≥1' in IEC.
Also known as: inclusive OR gate, OR logic gate, disjunction gate, OR function, Boolean OR.
What the OR Gate symbol means
The OR gate symbol represents a combinational logic element that performs the Boolean OR operation: its output Y is HIGH if any one or more of its inputs are HIGH, and LOW only when all inputs are simultaneously LOW. With two inputs A and B, the truth table is: 0+0=0, 0+1=1, 1+0=1, 1+1=1.
In a schematic or logic diagram, the OR gate symbol signals that the designer requires a logical disjunction — the circuit should respond (output HIGH) if any one of multiple conditions is met. OR gates appear in combinational logic, address decoders, flag aggregators, and interrupt-request arbitration circuits where any one of several events should trigger a response.
How to identify the OR Gate symbol
In ANSI/IEEE (IEEE Std 91/91a) the OR gate symbol has a distinctive curved body: flat on the left input side, curving outward to a pointed right output. The back (input) edge has a gentle inward curve. Two input lines (A and B) enter from the flat left; one output line (Out) exits from the pointed right tip. In IEC 60617-12 the OR gate is a plain rectangle with the qualifying symbol '≥1' inside, meaning 'output is active if one or more inputs are active'. The IEC rectangular form is used throughout European and international schematic practice.
Function in a circuit
The OR gate implements Boolean disjunction: output Y = A OR B (written A + B in Boolean algebra). The output is HIGH whenever at least one input is HIGH. In CMOS technology (e.g. 74HC32), the OR gate is typically built from a NOR gate followed by an inverter. Propagation delay for standard CMOS OR gates is approximately 5–15 ns. OR gates can be cascaded to create multi-input OR functions, or combined with AND/NOT gates to implement any combinational logic function.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 (Binary logic elements) defines the OR gate as a rectangle with the qualifying symbol '≥1' inside. The rectangle has straight edges and labelled input pins on the left and output pin on the right. |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2 / IEEE 315 and IEEE Std 91/91a define the OR gate as a curved shield shape: a pointed output end, a curved body, and a concave left edge at the inputs. This 'traditional' OR gate shape is the de-facto standard in North American and most educational schematics. |
| Key difference | The IEC symbol is a rectangle with '≥1' qualifier; the ANSI/IEEE symbol is the curved shield shape. Both represent the same Boolean function. IEC rectangular logic symbols are standard in industrial and European schematics; ANSI curved symbols dominate in North American, academic, and hobbyist contexts. |
Terminals / pins
| Pin | Name |
|---|---|
| a | A |
| b | B |
| out | Out |
Typical values
Logic levels: 0 (LOW, typically 0 V) and 1 (HIGH, typically 3.3 V or 5 V depending on logic family). Supply voltage: 2–6 V (74HC), 1.65–5.5 V (74LVC). Propagation delay: 5–15 ns at VCC = 5 V (74HC32). Fan-out: typically 10 (TTL), 50+ (CMOS). Number of inputs: 2 (standard), up to 8 on single-package ICs such as the 4072.
Where the OR Gate symbol is used
- Interrupt arbitration: any one of several interrupt sources driving a common processor IRQ line via an OR gate
- Address decoding: combining partial address lines to select a memory region when any of several addresses are active
- Alarm aggregation: merging multiple sensor fault signals so any single fault triggers a system alarm output
- Enable logic: allowing a device to be enabled from either of two control sources
- Boolean expression implementation: building sum-of-products (SOP) logic networks from AND and OR gates in PLDs and FPGAs
- Error flag propagation: OR-ing status bits from multiple modules to create a composite fault indicator
Example
In a home security microcontroller schematic, three door-sensor signals (front door, back door, window) each connect to an input of a 3-input OR gate (74HC4075); the OR gate output drives a microcontroller interrupt pin, so the processor is notified immediately if any single door or window is opened, without requiring the MCU to poll each sensor individually.
Key facts
- The OR gate implements Boolean disjunction: output Y = A + B; output is HIGH (1) when any one or more inputs are HIGH, and LOW (0) only when all inputs are simultaneously LOW.
- The ANSI/IEEE 315 OR gate symbol has a curved shield shape with a pointed output tip and a concave left (input) edge; the IEC 60617-12 symbol is a rectangle containing the qualifier '≥1'.
- Standard OR gate ICs include the 74HC32 (quad 2-input OR), 74HC4072 (dual 4-input OR), and 4071B CMOS (quad 2-input OR); the reference designator is U (e.g. U3).
- The OR gate has three terminals in its basic 2-input form: input A, input B (both on the left in schematics), and output Out (on the right).
- IEC 60617-12 and ANSI Y32.2/IEEE 315 both define the OR gate; the functional logic is identical but the glyph shapes differ: rectangle (IEC) versus curved shield (ANSI).
- An OR gate can be constructed from NAND gates or NOR gates (universal gates): A OR B = NOT(NOT A AND NOT B) using De Morgan's theorem.
- Propagation delay for a 74HC32 OR gate is approximately 7 ns at 5 V, making it suitable for logic frequencies up to tens of MHz.
- OR gates are the basis of sum-of-products (SOP) Boolean logic networks and are fundamental building blocks in PLDs, FPGAs, and ALUs.
Frequently asked questions
What does the OR gate symbol look like?
In ANSI/IEEE schematics, the OR gate symbol has a curved shield body: two input lines enter from the left (slightly concave edge) and one output exits from the pointed right tip. In IEC 60617-12 schematics, the OR gate is a rectangle with the qualifier symbol '≥1' written inside, indicating the output activates when one or more inputs are active.
What does the OR gate symbol mean in a logic diagram?
The OR gate symbol means the output is HIGH (logic 1) whenever at least one input is HIGH. It implements Boolean OR: Y = A + B. The output is LOW only when all inputs are LOW simultaneously. In circuit design it represents the condition 'any one of these events triggers a response'.
What is the truth table for an OR gate?
A 2-input OR gate truth table: A=0, B=0 → Y=0; A=0, B=1 → Y=1; A=1, B=0 → Y=1; A=1, B=1 → Y=1. The output is LOW only when both inputs are LOW. For N inputs, the output is LOW only when all N inputs are simultaneously LOW.
What is the difference between the IEC and ANSI OR gate symbols?
The IEC 60617-12 OR gate symbol is a rectangle with the qualifier '≥1' inside, indicating one-or-more active inputs. The ANSI Y32.2/IEEE 315 symbol is the traditional curved shield shape with a pointed output. Both represent the same Boolean OR function; IEC rectangular symbols are standard in European/industrial schematics, ANSI curved symbols in North American and educational contexts.
What is the designator for an OR gate?
The reference designator for an OR gate IC is U (per IEEE 315), appearing as U1, U2, etc. on a schematic. In logic diagrams that show individual gate symbols rather than IC packages, no separate designator is assigned to each gate; instead the IC package (e.g. 74HC32) carries the U designator and individual gates are referenced by pin numbers.
What standard defines the OR gate symbol?
The OR gate symbol is defined in IEC 60617-12 (Binary logic elements) for the rectangular-with-qualifier IEC form, and in ANSI Y32.2 / IEEE 315 and IEEE Std 91/91a for the curved shield ANSI form. Both international standards define the OR function identically; only the graphical representation differs.
What is the difference between an OR gate and a NOR gate?
An OR gate outputs HIGH when any input is HIGH. A NOR gate is an OR gate followed by an inverter: its output is LOW when any input is HIGH, and HIGH only when all inputs are LOW. In ANSI schematics, the NOR gate symbol is identical to the OR gate shape but with a small circle (bubble) at the output tip representing inversion.
Place the OR Gate symbol on a wiring diagram or schematic in the free online circuit diagram maker — no download required.