PLL Block Symbol
Definition: The PLL Block symbol represents a Phase-Locked Loop — a closed-loop feedback circuit used in electronic and RF schematics to denote a system that locks the frequency and phase of its voltage-controlled oscillator output to a reference input signal, producing a stable, synchronised output frequency that is a precise integer or fractional multiple of the reference, as defined in IEEE 1139 (standard definitions of physical quantities for fundamental frequency and time metrology); the designator is U or PLL.
Also known as: phase-locked loop, PLL, clock synthesizer, frequency synthesizer, PLL IC, clock PLL, digital PLL, DPLL, charge-pump PLL, CPLL.
What the PLL Block symbol means
The PLL Block symbol denotes an active feedback system comprising three core subsystems: a phase detector (PD) that compares the phase of the reference input to the divided VCO output; a low-pass loop filter (LPF) that smooths the phase-detector error voltage; and a voltage-controlled oscillator (VCO) whose frequency is steered by the filter output to eliminate the phase error. An optional programmable frequency divider (÷N) in the feedback path multiplies the output frequency relative to the reference, enabling frequency synthesis.
In a schematic or block diagram, the PLL Block symbol communicates that the REF input drives a synchronisation system whose OUT terminal provides a clock or carrier signal that is phase-coherent with the reference. Engineers reading the diagram understand that jitter, phase noise, lock time, and loop bandwidth are the key performance parameters, and that the VCC and GND pins supply the active devices inside the loop. The four-pin model (REF, OUT, VCC, GND) is the compact representation; detailed schematics may expand the block to show individual PD, LPF, VCO, and divider subsymbols.
How to identify the PLL Block symbol
The PLL Block symbol is a rectangle labelled 'PLL' or 'Phase-Locked Loop', with four terminals: REF (reference frequency input) entering from the left; OUT (VCO/synthesised output) exiting to the right; VCC (positive supply) at the top centre; and GND (ground) at the bottom centre. More detailed representations subdivide the rectangle into three or four labelled sub-blocks — PD | LPF | VCO — with the ÷N divider shown in the feedback path returning from OUT back to PD. The feedback arrow is the key visual cue that distinguishes a PLL from a plain oscillator or filter block.
Function in a circuit
The PLL generates a stable, phase-coherent output frequency by continuously comparing the phase of a divided version of its VCO output to a reference clock and feeding the error signal back to tune the VCO. This allows the PLL to multiply a low-frequency, low-jitter reference (such as a 10 MHz TCXO) up to a high-frequency output (such as 2.4 GHz) while maintaining phase coherence, clean spectral purity, and fast acquisition. The same feedback principle enables clock recovery from a data stream, frequency demodulation of FM/PM signals, and motor synchronisation.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617 does not define a dedicated PLL glyph; the PLL Block is represented using the general functional-block rectangle from IEC 60617-02 (binary logic elements) with labelled terminals. The relevant IEC standard for PLL performance and phase noise is IEC 60267 (measurement of frequency stability) and IEEE 1139. |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2 / IEEE 315-1975 similarly uses the labelled functional-block rectangle for PLL blocks. IEEE 1139-2008 (Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology) provides the framework for PLL phase-noise and jitter specifications. |
| Key difference | Identical in both IEC and ANSI/IEEE — both use a labelled rectangle with terminal identifiers. The PLL block has no unique IEC or ANSI glyph; symbol identity is determined entirely by the label and pin names. |
Terminals / pins
| Pin | Name |
|---|---|
| ref | REF |
| out | OUT |
| vcc | VCC |
| gnd | GND |
Typical values
Reference frequency: 1 Hz to 100 MHz (typical); output frequency: 10 kHz to 10 GHz+ (RF VCO) or 1 MHz to 800 MHz (CMOS clock PLL); supply voltage VCC: 1.8 V to 5 V; phase noise: −80 dBc/Hz to −150 dBc/Hz at 1 kHz offset; lock time: microseconds to milliseconds; loop bandwidth: 1 kHz to 10 MHz.
Where the PLL Block symbol is used
- RF transceivers (Wi-Fi, Bluetooth, cellular) where the PLL synthesises the carrier frequency from a crystal reference
- Microprocessor and SoC clock distribution, multiplying a 25 MHz board reference to 1 GHz+ core clock
- Television and video equipment recovering the colour-burst reference clock from a composite video signal
- Motor drive synchronisation systems locking drive output frequency to a grid reference for regenerative braking
- Software-defined radio (SDR) front ends synthesising tunable LO frequencies across wide frequency spans
- Precision timing and synchronisation equipment (GPS disciplined oscillators, IEEE 1588 PTP hardware)
Example
In an RF transceiver schematic, the PLL Block appears between a 26 MHz TCXO reference oscillator and the power amplifier stage; the REF pin is driven by the 26 MHz crystal signal, the ÷N divider is programmed to 92 (via SPI bus), and the OUT pin produces 2392 MHz ± 50 ppm — the transmit carrier — while the loop filter capacitors connected between the VCO control voltage node and ground set the 100 kHz loop bandwidth and −95 dBc/Hz phase noise at 1 kHz offset.
Key facts
- The PLL Block symbol is a labelled rectangle with four terminals: REF (reference input), OUT (synthesised output), VCC (supply), and GND; it follows the IEC 60617-02 general functional-block convention.
- The PLL designator in schematics is U or PLL, following IEEE 315-1975 functional-block labelling conventions.
- A Phase-Locked Loop contains three core subsystems: a phase detector (PD), a low-pass loop filter (LPF), and a voltage-controlled oscillator (VCO), often with a programmable ÷N frequency divider in the feedback path.
- The output frequency of a PLL with a ÷N divider equals N times the reference frequency (f_out = N × f_ref), enabling frequency multiplication from a low-frequency stable reference.
- Phase noise — the spectral purity of the output clock, measured in dBc/Hz at a given offset frequency — is the primary figure of merit for a PLL in RF and precision timing applications.
- IEEE 1139-2008 provides standard definitions for frequency stability, phase noise, and jitter, which are the key parameters specified on PLL data sheets and schematics.
- PLLs are used in four major application domains: frequency synthesis (RF), clock multiplication (digital ICs), clock recovery (serial data links), and signal demodulation (FM/PM receivers).
- A locked PLL has zero steady-state phase error at DC (Type II loop) or a fixed phase error (Type I loop); the lock indication pin found on many PLL ICs confirms the feedback loop has acquired lock.
Frequently asked questions
What does the PLL Block symbol mean in a circuit diagram?
The PLL Block symbol represents a Phase-Locked Loop — a closed-loop feedback circuit that synchronises the frequency and phase of its internal voltage-controlled oscillator to a reference input signal. It is used in RF, digital clock, and signal recovery applications to produce a stable, phase-coherent output frequency.
What does the PLL Block symbol look like?
The PLL Block symbol is a rectangle labelled 'PLL' with four terminals: REF (reference input, left), OUT (output, right), VCC (supply, top), and GND (ground, bottom). Detailed schematics subdivide the rectangle into PD, LPF, and VCO sub-blocks with a feedback arrow from OUT back to PD.
What are the three main subsystems inside a PLL?
The three core subsystems of a PLL are: (1) a Phase Detector (PD) that measures the phase difference between the reference and the feedback signal; (2) a Low-Pass Loop Filter (LPF) that smooths the error voltage; and (3) a Voltage-Controlled Oscillator (VCO) whose frequency is tuned by the filter output to eliminate the phase error.
What is the designator letter for a PLL block?
The PLL Block is designated U (for integrated circuit functional block) in schematics, following IEEE 315-1975 and ANSI Y32.2. It may also be labelled PLL followed by a number (e.g., PLL1) as a functional block designator.
Is there a specific IEC or ANSI symbol standard for PLL blocks?
No dedicated IEC 60617 or ANSI Y32.2/IEEE 315 glyph exists for PLL blocks. Both standards use the general functional-block rectangle convention (IEC 60617-02 / IEEE 315 section 3.20); the block is identified entirely by its 'PLL' label and pin names.
How does a PLL multiply frequency?
A PLL multiplies frequency by inserting a programmable ÷N frequency divider in the feedback path between the VCO output and the phase detector. When the loop locks, the phase detector sees the reference frequency and the divided VCO frequency as equal, so the VCO must run at N times the reference frequency (f_out = N × f_ref).
What is phase noise and why does it matter on a PLL symbol page?
Phase noise is the short-term frequency instability of an oscillator, measured as the ratio of noise power in a 1 Hz band at a specified offset from the carrier to the carrier power, expressed in dBc/Hz. It is the key performance specification for PLL-based frequency synthesisers: low phase noise means a cleaner, more spectrally pure output clock, which is critical for RF receiver sensitivity and ADC dynamic range.
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