Phase Detector Symbol
Definition: The Phase Detector symbol represents an analog or digital circuit block — a key sub-component of a Phase-Locked Loop (PLL) — that compares the phase (and optionally frequency) of two input signals (In1 and In2) and produces an output voltage or current proportional to the phase difference between them, as standardised in functional block diagram notation per IEC 60617-02 and IEEE 315.
Also known as: phase comparator, phase-frequency detector, PFD, XOR phase detector, phase discriminator, PLL phase detector.
What the Phase Detector symbol means
The Phase Detector symbol represents a circuit that measures the phase difference between two periodic signals — typically a reference signal (In1) and a feedback signal (In2) from a voltage-controlled oscillator (VCO). The output of the phase detector is a voltage or current signal whose magnitude is proportional to the phase difference; this output is filtered and used to control the VCO to lock the loop.
In PLL-based circuit diagrams, the phase detector symbol is the first block in the PLL chain, accepting the reference frequency input and the VCO feedback signal. Phase detectors are fundamental to frequency synthesis, clock recovery, demodulation of FM/PM signals, and motor speed control. Common implementations include XOR-gate phase detectors (for 90° lock point), edge-triggered phase-frequency detectors (PFDs, which also detect frequency difference), and analog multiplier (mixer) phase detectors.
How to identify the Phase Detector symbol
The Phase Detector symbol is drawn as a rectangular block with two input terminals on the left (In1 and In2, each accepting a periodic signal) and one output terminal on the right (Out, providing the phase-difference error signal). The block is labelled 'Phase Detector', 'PD', or 'PFD' (Phase-Frequency Detector). In detailed schematics, the phase detector may be shown as an XOR gate (for digital XOR-type), a set-reset flip-flop pair (for PFD type), or an analog multiplier symbol depending on the implementation type.
Function in a circuit
The phase detector generates an output proportional to the phase difference (Δφ) between its two input signals. For an XOR-type phase detector, the output is a pulse-width-modulated signal whose duty cycle increases with phase difference (0° = 0% duty, 90° = 50% duty, 180° = 100% duty), with a quiescent lock point at 90°. For a phase-frequency detector (PFD), the output is a charge-pump current (Up or Down pulses) proportional to phase and frequency error, with a quiescent lock point at 0° phase difference and zero frequency error. The filtered output drives a VCO: if In2 lags In1, the VCO is sped up; if In2 leads In1, the VCO is slowed down, completing the negative feedback loop.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-02 defines block diagram symbol conventions; the phase detector is represented as a rectangular functional block with labelled terminals. IEC 61164 and IEC 60168 cover PLL applications in telecommunications, within which the phase detector block is a defined sub-system. |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2 / IEEE 315 represents the phase detector as a labelled rectangular block in system-level diagrams. IEEE 1139 (Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology) provides terminology for phase noise and phase comparison. IEEE 1394 and related standards use PLL phase detectors in clock recovery circuits. |
| Key difference | IEC 60617-02 and ANSI Y32.2/IEEE 315 both represent the phase detector as a rectangular block labelled 'PD' or 'Phase Detector'. No significant symbol difference exists between the two standards for this functional block. Internal implementation details (XOR gate, flip-flop PFD, or analog multiplier) are drawn using standard gate or component symbols specific to each implementation. |
Terminals / pins
| Pin | Name |
|---|---|
| in1 | In1 |
| in2 | In2 |
| out | Out |
Typical values
Input frequency range: DC to several GHz depending on implementation (XOR: DC–100 MHz; PFD: DC–1 GHz; analog multiplier: DC–microwave). Output voltage: proportional to phase difference; typically 0 to Vsupply (digital) or ±Vsupply/2 (analog). Phase detection range: ±π radians (XOR type), ±2π radians (PFD type). Gain (Kd): typically 0.3–2 V/rad for analog types. Input impedance: high (CMOS gate input or 50 Ω terminated for RF types).
Where the Phase Detector symbol is used
- PLL frequency synthesisers: phase detector compares VCO output (divided) against crystal reference to lock output frequency
- Clock and data recovery (CDR): phase detector recovers clock phase from serial data stream transitions
- FM and PM demodulation: analog multiplier phase detector extracts audio from frequency- or phase-modulated RF carriers
- Motor speed control PLLs: phase detector compares motor tachometer pulses against reference frequency to maintain constant speed
- Digital clock synchronisation: PFD synchronises system clocks across PCBs in high-speed digital systems (DDR, SerDes)
- Phase noise measurement: phase detector in a carrier cancellation scheme measures the relative phase noise between two signal sources
Example
In a PLL-based frequency synthesiser block diagram, the phase detector symbol (labelled PD) has In1 connected to a 10 MHz crystal oscillator reference and In2 connected to the divided output of the VCO (÷N divider). The PD output feeds a low-pass loop filter, whose filtered output controls the VCO. When the VCO frequency (÷N) matches the reference, the phase detector output stabilises at the quiescent point, the loop is locked, and the VCO outputs N×10 MHz with low phase noise.
Key facts
- A phase detector compares the phase of two input signals (In1 = reference, In2 = feedback) and produces an output proportional to their phase difference, used as the error-signal generator in Phase-Locked Loop (PLL) circuits.
- The three terminals of the phase detector symbol are: In1 (reference signal input), In2 (feedback/VCO signal input), and Out (phase-difference error output).
- Three common phase detector types exist: XOR-gate (digital, lock at 90°), phase-frequency detector/PFD (digital flip-flop pair, lock at 0°, can also detect frequency difference), and analog multiplier (linear, used in analog PLLs and FM demodulators).
- A Phase-Frequency Detector (PFD) can detect both phase error and frequency error between inputs, making it superior to a simple XOR phase detector for large initial frequency offsets — PFDs are standard in modern synthesiser ICs such as the CD4046 and ADF4xx series.
- Phase detector gain (Kd) — output voltage per radian of phase difference — is a critical PLL parameter; typical values range from 0.3 V/rad to 2 V/rad for integrated CMOS phase detectors.
- IEC 60617-02 and ANSI Y32.2/IEEE 315 both represent the phase detector as a labelled rectangular functional block; no standard-specific glyph distinguishes IEC from ANSI representations for this block.
- XOR phase detectors have a detection range of ±π radians and produce a 50% duty-cycle output at the 90° quadrature lock point; they require input signals with exactly 50% duty cycle for correct operation.
Frequently asked questions
What does the phase detector symbol look like?
The phase detector symbol is a rectangular block labelled 'Phase Detector', 'PD', or 'PFD' with two input terminals on the left (In1 = reference, In2 = feedback/VCO) and one output terminal on the right (Out = phase-difference error signal). In detailed digital PLL schematics it may be drawn as an XOR gate or a pair of D flip-flops with charge-pump outputs depending on the implementation type.
What does a phase detector do?
A phase detector measures the phase difference between two periodic input signals and produces an output voltage or current proportional to that difference. In a Phase-Locked Loop (PLL), this output is filtered and used to control a voltage-controlled oscillator (VCO) to drive the phase difference to zero, locking the VCO output frequency to a multiple of the reference input frequency.
What is the difference between a phase detector and a phase-frequency detector?
A phase detector (e.g. XOR type) can only measure phase differences within its detection range (±π radians for XOR) and cannot detect frequency differences — if the two inputs differ significantly in frequency, the loop may not acquire lock. A phase-frequency detector (PFD) uses edge-triggered flip-flops to detect both phase and frequency differences over an unlimited range, allowing the PLL to acquire lock from large initial frequency offsets. PFDs are the standard choice in modern frequency synthesiser ICs.
What is the output of a phase detector?
The output of a digital XOR phase detector is a pulse-width-modulated signal whose average voltage increases with increasing phase difference (0 V at 0° difference, Vdd/2 at 90°, Vdd at 180°). A PFD produces Up and Down current pulses driving a charge pump, generating an average current proportional to phase error. An analog multiplier phase detector produces a DC voltage proportional to cos(Δφ).
What standard defines the phase detector symbol?
IEC 60617-02 (Binary Logic Elements and block diagram conventions) and ANSI Y32.2/IEEE 315 both define the phase detector as a rectangular functional block symbol with labelled input/output terminals. There is no dedicated glyph; the block is identified by its text label ('PD', 'PFD', or 'Phase Detector'). Internal circuit symbols follow IEC 60617-12 (logic gates) or IEEE 315 as appropriate for the implementation.
What circuits use a phase detector?
Phase detectors are used in Phase-Locked Loops (PLLs) for frequency synthesis, clock and data recovery (CDR), FM/PM demodulation, motor speed control, and clock synchronisation in digital systems. The phase detector is the error-sensing element in all PLL topologies, comparing the reference frequency phase against the VCO or DCO feedback to generate the control signal that closes the loop.
What is phase detector gain (Kd)?
Phase detector gain (Kd) is the ratio of the detector output voltage (or charge-pump current) to the input phase difference in radians — expressed in V/rad or A/rad. It is a critical PLL loop parameter that, along with VCO gain (Kvco) and loop filter response, determines loop bandwidth, stability, and phase noise. Typical CMOS PFD/charge-pump Kd values range from 100 µA/2π (charge-pump current ÷ 2π) to several mA/2π.
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