SR Latch Symbol
Definition: The SR Latch symbol represents a basic bistable sequential logic element drawn as a labeled rectangle with Set (S) and Reset (R) inputs and complementary outputs Q and Q̄ (Q-bar), denoting a fundamental memory cell that stores one bit of digital state — Set input drives Q HIGH, Reset input drives Q LOW — as defined in IEC 60617-12 (binary logic elements) and ANSI Y32.2/IEEE 315.
Also known as: set-reset latch symbol, SR bistable symbol, RS latch symbol, set-reset flip-flop symbol, SR memory cell symbol.
What the SR Latch symbol means
The SR Latch symbol represents the simplest bistable (two-stable-state) digital memory element. Unlike combinational logic gates whose output is determined solely by current inputs, the SR latch retains (latches) its last output state even after the inputs return to their inactive state. When the S (Set) input is driven HIGH, the Q output goes HIGH and Q̄ (Q-bar) goes LOW. When the R (Reset) input is driven HIGH, Q goes LOW and Q̄ goes HIGH. When both S and R are LOW, the latch holds its previous state — this is its memory action. The simultaneously-HIGH (S=1, R=1) input combination is the forbidden state, as it drives both Q and Q̄ to the same logic level, producing an indeterminate state when both inputs return LOW.
In digital circuit diagrams, the SR latch symbol appears as the core element of more complex sequential circuits: D flip-flops, JK flip-flops, counters, registers, and state machines all contain SR latches internally. The SR latch is also used directly in switch debounce circuits, sensor latch applications, and simple alarm memory circuits where a condition must be remembered until manually reset.
How to identify the SR Latch symbol
The SR Latch symbol is drawn as a rectangle with the label 'S' near the upper-left input pin and 'R' near the lower-left input pin, indicating the Set and Reset inputs. On the right edge, 'Q' labels the upper output and a line over Q (Q̄) labels the lower output — the overbar is sometimes shown as a bubble (small circle) on the output pin. Two wires exit the left side (S at top, R at bottom) and two wires exit the right side (Q at top, Q̄ at bottom). The S/R input pair and complementary Q/Q̄ output pair are the identifying features that distinguish the SR latch from a D flip-flop (which has a single D input and CLK) and from an AND or OR gate (which has no feedback-implied memory).
Function in a circuit
The SR latch stores a single bit of logic state using feedback between two cross-coupled NOR gates (or NAND gates for active-low SR). In the NOR implementation, applying S=1 forces Q=1 (set state); applying R=1 forces Q=0 (reset state). The cross-coupled feedback ensures the output remains stable after the input returns to inactive. In the NAND (active-low) implementation, inputs are inverted: S̄=0 sets, R̄=0 resets. The SR latch has no clock input — it is level-sensitive (asynchronous), meaning it responds immediately to input changes, which makes it fast but also susceptible to glitches. For clocked (synchronous) operation, a gated SR latch or a D flip-flop is used.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 defines graphical symbols for binary logic elements including bistable circuits. The IEC symbol for an SR latch is a rectangle with 'S' and 'R' input labels and 'Q' and complemented-Q output labels, conforming to IEC logic symbol conventions (rectangular shapes for all logic functions). |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2-1975 (IEEE 315) and IEEE Std 91-1984 (graphic symbols for logic functions) define the SR latch using the same rectangular symbol with S, R, Q, and Q̄ labels. IEEE 91a-1991 (supplement to IEEE 91) provides additional notation for complex sequential elements. Both IEC and ANSI use identical rectangular notation for SR latches. |
| Key difference | No glyph difference exists between IEC 60617-12 and ANSI Y32.2/IEEE 315 for the SR latch symbol. Both use a labeled rectangle with S/R inputs and Q/Q̄ outputs. The complement output (Q̄) may be indicated with an overbar, a bubble on the pin, or the text 'Q-bar' depending on the drawing tool. |
Terminals / pins
| Pin | Name |
|---|---|
| s | S |
| r | R |
| q | Q |
| qn | Q̅ |
Typical values
Logic family supply voltage: 1.8 V, 3.3 V, or 5 V (CMOS); 5 V (TTL). Propagation delay: 1–10 ns (CMOS, e.g., 74HC279); setup/hold constraints: none (asynchronous latch). Forbidden state: S=1 AND R=1 simultaneously (indeterminate). Power consumption: microamps (CMOS static). Example ICs: 74HC279 (quad SR latch), 74LS279.
Where the SR Latch symbol is used
- Switch debounce circuits where an SR latch remembers the first edge of a mechanical switch bounce sequence, providing a clean single transition output
- Alarm memory and fault-latch circuits that store a fault condition (S input from sensor) until manually reset (R input from operator button)
- D flip-flop and JK flip-flop internal implementations where cross-coupled SR latches form the master and slave stages
- Priority arbiter circuits where the first of two competing events latches an output, locking out the other until reset
- Data storage in SRAM cells where each bit is stored by a pair of cross-coupled inverters forming an SR-latch equivalent
- Interlock and permissive logic circuits where a safety condition must be confirmed (set) before a machine can run, and a fault resets the permissive
Example
In a pushbutton debounce circuit, an SR latch symbol has the S input connected to a pushbutton that pulls it HIGH when pressed and R connected to a second contact of the same button that pulls HIGH when released. On the first bounce contact, S goes HIGH and Q latches HIGH cleanly; subsequent S and R bounces do not affect Q (since S and R cannot both be HIGH simultaneously with this circuit topology). The clean Q output goes to a microcontroller interrupt pin, triggering a single count per button press.
Key facts
- The SR Latch symbol has four pins: S (Set, pin id: s), R (Reset, pin id: r), Q (output, pin id: q), and Q̄ (complementary output, pin id: qn), as defined in IEC 60617-12 and ANSI Y32.2/IEEE 315.
- An SR latch is bistable — it retains its last output state (Q HIGH or Q LOW) indefinitely after inputs return to inactive (both S=0, R=0), making it the simplest digital 1-bit memory element.
- Applying S=1 (with R=0) sets Q to HIGH and Q̄ to LOW. Applying R=1 (with S=0) resets Q to LOW and Q̄ to HIGH. Both inputs LOW holds the current state.
- The forbidden state S=1, R=1 simultaneously drives both Q and Q̄ to the same logic level (both LOW in NOR implementation, both HIGH in NAND implementation), creating an indeterminate state when both return to inactive.
- SR latches are asynchronous (no clock input) — they respond immediately to input changes, making them faster but less predictable than clocked flip-flops in synchronous digital systems.
- A cross-coupled NOR gate SR latch (active-HIGH inputs) and a cross-coupled NAND gate SR latch (active-LOW inputs, also called S̄R̄ latch) are the two basic implementations; both produce the same logical behaviour with inverted input polarity.
- The 74HC279 is a widely used quad SR latch integrated circuit, implementing four independent SR latches in a 16-pin DIP or SOIC package, with supply voltage 2–6 V.
- SR latches form the core of all flip-flop and register circuits — a D flip-flop is constructed from a gated SR latch with an inverter connecting D to both S and R through an enable gate.
Frequently asked questions
What does the SR latch symbol look like in a circuit diagram?
The SR Latch symbol is a rectangle with 'S' labeling the upper-left input pin (Set) and 'R' labeling the lower-left input pin (Reset). On the right side, 'Q' labels the upper output and Q̄ (Q with an overbar, or a bubble on the pin) labels the lower complementary output. Two wires enter from the left (S and R) and two exit from the right (Q and Q̄).
What does an SR latch do in a digital circuit?
An SR latch stores one bit of digital state. Pulsing the S (Set) input HIGH drives the Q output HIGH and holds it there even after S returns LOW. Pulsing the R (Reset) input HIGH drives Q LOW and holds it. When both inputs are LOW, the latch holds its last state indefinitely — this is the memory action. It is the simplest bistable (two-stable-state) circuit element.
What is the forbidden state of an SR latch?
The forbidden state of an SR latch is S=1 AND R=1 simultaneously. In a NOR-gate SR latch, this drives both Q and Q̄ to LOW at the same time, violating the required complementary relationship. When both inputs return to LOW from this state, the output is indeterminate — it depends on which gate responds slightly faster, producing unpredictable behaviour.
What is the difference between an SR latch and a D flip-flop symbol?
An SR latch symbol has two independent inputs (S and R) and no clock input, making it asynchronous — it responds immediately to input changes. A D flip-flop symbol has one data input (D) and a clock input (CLK); the output only changes on the active clock edge. An SR latch is simpler but asynchronous; a D flip-flop is synchronous and safer to use in clocked digital systems.
What is the difference between an SR latch and an RS latch?
SR latch and RS latch refer to the same bistable circuit. The naming convention (SR vs RS) is a matter of preference — 'SR' emphasises that Set precedes Reset alphabetically; 'RS' is an older convention. Both names identify the same NOR or NAND cross-coupled bistable with Set and Reset inputs and complementary Q/Q̄ outputs.
What standard defines the SR latch symbol?
IEC 60617-12 (graphical symbols for diagrams — binary logic elements) defines the SR latch symbol as a rectangle with S/R inputs and Q/Q̄ outputs. ANSI Y32.2-1975 (IEEE 315) and IEEE Std 91-1984 define the same rectangular symbol. Both IEC and ANSI conventions are identical for this element.
What is the practical application of an SR latch in a circuit?
The most common practical application of an SR latch is switch debounce: a mechanical pushbutton bounces 10–100 times when pressed, but an SR latch responds to the first transition and holds its output stable through all subsequent bounces, delivering a clean single digital edge to a microcontroller. SR latches are also used in alarm memory circuits, permissive interlocks, and as the core storage elements inside D flip-flops and SRAM cells.
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