D Flip-Flop Symbol
Definition: The D Flip-Flop symbol represents an edge-triggered bistable storage element that captures the logic level present at its Data input (D) on the active clock edge and holds that value at its output (Q) until the next active clock edge, defined under IEEE Std 91-1984 / IEC 60617-12 for logic element symbols.
Also known as: DFF, D-type flip-flop, data flip-flop, delay flip-flop, D latch (edge-triggered).
What the D Flip-Flop symbol means
The D Flip-Flop symbol denotes a fundamental sequential logic building block that stores one bit of information. On each active clock edge (typically the rising edge), the flip-flop samples the D input and transfers its value to Q, simultaneously updating Q̅ (Q-bar) to the complementary state. Between clock edges the output is latched and stable regardless of changes to D.
In digital design the D flip-flop is the canonical register element used in shift registers, pipeline stages, state machines, and synchronous counters. The symbol's clock input with its characteristic triangle mark signals edge-triggered behaviour, distinguishing it from a level-sensitive latch.
How to identify the D Flip-Flop symbol
The D Flip-Flop symbol is a rectangle (logic block) with four pins: D (data input, left side), CLK (clock input, left side with a small triangle pointing right to indicate edge-triggering), Q (output, right side), and Q̅ (complemented output, right side). The triangle on the CLK input is the key distinguishing mark of an edge-triggered device. A bubble (small circle) on Q̅ indicates active-low complemented output. If a bubble also appears on the CLK triangle, the flip-flop is negative-edge (falling-edge) triggered.
Function in a circuit
The D flip-flop captures the D input level on the active clock edge and presents it at Q. The complementary output Q̅ is always the logical inverse of Q. The single-rail data input (D) eliminates the forbidden state of the SR latch, making the D flip-flop the preferred storage element in synchronous digital systems. Set (S) and Reset (R) override inputs may be present on extended versions for asynchronous initialisation.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 (Binary Elements) defines the D flip-flop as a rectangle with a 'D' input, a dynamic (triangle) clock input, Q and Q̅ outputs. The triangle on the CLK input indicates edge-triggering. |
|---|---|
| ANSI/IEEE 315 | IEEE Std 91-1984 (ANSI/IEEE 91) and IEEE Std 91a-1991 define the distinctive-shape and rectangular-outline logic symbols. The D flip-flop uses the same rectangle-with-triangle-clock convention as IEC. |
| Key difference | IEC 60617-12 and IEEE Std 91 use essentially identical rectangular block symbols for the D flip-flop with triangle clock indicator. The main variation in practice is whether the device has asynchronous preset/clear inputs (S̅ and R̅) shown as additional bubbled inputs. |
Terminals / pins
| Pin | Name |
|---|---|
| d | D |
| clk | CLK |
| q | Q |
| qn | Q̅ |
Typical values
Logic supply voltage: 1.8 V, 3.3 V, or 5 V depending on logic family (CMOS/TTL). Propagation delay t_pd: 1–15 ns typical for 74HC/74LS series. Setup time t_su: 2–10 ns. Hold time t_h: 0–5 ns. Maximum clock frequency f_max: up to 200 MHz for standard CMOS logic.
Where the D Flip-Flop symbol is used
- Shift registers (serial-in, serial-out) built by cascading multiple D flip-flops clocked together.
- Pipeline registers in microprocessors and DSPs that hold intermediate computation results between clock cycles.
- Synchronous finite-state machines where each flip-flop stores one bit of the current state.
- Synchronisers that transfer asynchronous input signals into a synchronous clock domain.
- Frequency dividers where the Q output is fed back to D via an inverter, halving the clock frequency.
- Edge-to-level converters that capture a pulse event and hold it until the processor reads and clears the flag.
Example
In a 4-bit serial-in parallel-out shift register, four D flip-flops are chained so that the Q output of each feeds the D input of the next. All CLK inputs share a common clock line. On each rising clock edge, the bit at the first D input shifts one position right across the chain; after four clock cycles the full 4-bit word appears simultaneously on Q0–Q3.
Key facts
- The D Flip-Flop captures the D input on the active clock edge (typically rising) and holds that value at Q until the next active clock edge, storing one bit of data.
- The four standard pins are D (data input), CLK (clock, edge-triggered, marked with a triangle), Q (output), and Q̅ (complemented output, always the logical inverse of Q).
- The triangle symbol on the CLK input is the key distinguishing mark of an edge-triggered flip-flop; without the triangle, the symbol represents a level-sensitive D latch.
- IEC 60617-12 and IEEE Std 91-1984 / ANSI Y32.14 both define the D flip-flop symbol as a rectangle with a triangle clock input; the two standards use essentially the same glyph.
- A D flip-flop eliminates the forbidden state of the SR latch by having only one data input; D = 0 sets Q = 0, D = 1 sets Q = 1 on the clock edge.
- Setup time (t_su) and hold time (t_h) constraints must be met for reliable operation: D must be stable for t_su before the clock edge and t_h after it.
- Cascading D flip-flops with the Q output fed back to D through an inverter creates a divide-by-2 frequency divider, producing a square wave at half the clock frequency.
Diagrams that use this symbol
Frequently asked questions
What does the D flip-flop symbol look like?
The D flip-flop symbol is a rectangle with four pins: D (data in, left), CLK (clock in, left, marked with a small rightward-pointing triangle), Q (output, right), and Q̅ (inverted output, right, sometimes with a bubble). The triangle on the clock input identifies it as an edge-triggered device.
What does the D in D flip-flop stand for?
The D stands for Data (sometimes also called Delay because the output follows the input with a one-clock-cycle delay). The single D input eliminates the indeterminate state of the SR latch by presenting only one binary choice to the storage element on each clock edge.
What is the difference between a D flip-flop and a D latch?
A D flip-flop is edge-triggered: it samples D only at the moment of the active clock edge and ignores D between edges. A D latch is level-sensitive: it is transparent (Q follows D) whenever the enable signal is high and opaque when the enable is low. The edge-triggered flip-flop is safer in synchronous designs because its output cannot change unexpectedly mid-clock-cycle.
What are the pins of a D flip-flop?
The standard D flip-flop pins are: D (data input), CLK (clock input, edge-triggered), Q (non-inverted output), and Q̅ (inverted output). Extended versions add asynchronous Set (S̅) and Reset (R̅) inputs for initialisation, active-low and indicated by a bubble on the pin.
What is the IEC symbol for a D flip-flop?
IEC 60617-12 defines the D flip-flop as a labelled rectangle (distinctive binary-element shape) with a 'D' label on the data input, a small triangle on the clock input to indicate edge-triggering, and Q / Q̅ outputs. IEEE Std 91-1984 uses the same rectangular convention.
How does a D flip-flop divide the clock frequency?
Connecting Q̅ back to the D input makes the flip-flop toggle on every rising clock edge. Because Q changes state every clock cycle, the Q output completes one full cycle for every two clock cycles—producing a square wave at exactly half the input clock frequency (divide-by-2 circuit).
What is setup time and hold time for a D flip-flop?
Setup time (t_su) is the minimum time the D input must be stable before the active clock edge for the flip-flop to reliably capture the data. Hold time (t_h) is the minimum time D must remain stable after the clock edge. Violating either constraint can cause metastability—an output that takes an unpredictably long time to settle to a valid logic level.
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