T Flip-Flop Symbol
Definition: The T Flip-Flop symbol represents a Toggle flip-flop — a clocked sequential logic element that changes (toggles) its output state on every active clock edge when the T (Toggle) input is HIGH, and holds its current state when T is LOW, producing complementary outputs Q and Q-bar; it is standardised in IEEE 91A / ANSI Y32.14 (logic symbols) and is fundamental to frequency division and binary counter circuits.
Also known as: toggle flip-flop, T-FF, divide-by-2 flip-flop, frequency divider cell, 1-bit counter.
What the T Flip-Flop symbol means
The T Flip-Flop symbol denotes a single-bit memory element that can be commanded to toggle its stored state on every clock edge when its T input is asserted. When T = 1, each rising (or falling, depending on implementation) clock edge causes Q to change from 0 to 1 or from 1 to 0. When T = 0, the clock is ignored and Q retains its previous value. The complementary output Q-bar (Qn) is always the logical inverse of Q.
The T flip-flop is the most natural building block for binary counters and frequency dividers. Connecting Q-bar back to T permanently holds T = 1, making the flip-flop toggle on every clock edge and producing a Q output at exactly half the input clock frequency — making one T flip-flop a divide-by-2 circuit. Cascading N flip-flops divides the frequency by 2^N.
How to identify the T Flip-Flop symbol
The T Flip-Flop symbol is drawn as a rectangle with four labelled terminals: T (Toggle input) and CLK (Clock input) on the left side, and Q and Qn (Q-bar, the complementary output) on the right side. The CLK input often has a small triangle (edge-trigger indicator) drawn inside the rectangle at the clock terminal to indicate that the flip-flop responds to a clock edge rather than a clock level. In some representations a bubble (inversion circle) appears at CLK for falling-edge triggered variants.
Function in a circuit
A T flip-flop stores one bit of state (0 or 1) in its Q output. On each active clock edge: if T = 1, Q changes to the opposite state (toggle); if T = 0, Q holds its current value (no change). The Qn output is always the complement of Q. By connecting Q or Qn back to T, the flip-flop divides the clock frequency by 2. In binary ripple counters, N cascaded T flip-flops count clock pulses from 0 to 2^N − 1 in binary.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 (binary logic elements) specifies the rectangular logic symbol for a toggle flip-flop with T, CLK, Q, and Qn terminals; the clock input is marked with a dynamic indicator (triangle) inside the rectangle for edge-triggered operation. IEC uses the designation 'T' for the toggle input. |
|---|---|
| ANSI/IEEE 315 | IEEE 91A / ANSI Y32.14 defines the rectangular distinctive shape for the T flip-flop, identical to the IEC rectangular form with T, C1 (clock), Q, and Q̄ labels. The edge-trigger indicator is a small triangle at the clock input. Both IEC and ANSI use the same rectangular symbol format for digital logic elements. |
| Key difference | IEC 60617-12 and IEEE 91A / ANSI Y32.14 use identical rectangular block symbols for the T flip-flop with edge-trigger indicator at CLK. Pin labelling may differ slightly (C1 vs CLK for the clock, Q̄ vs Qn for the complemented output) but the glyph is the same. Older ANSI distinctive-shape symbols also existed but the rectangular form is now standard. |
Terminals / pins
| Pin | Name |
|---|---|
| t | T |
| clk | CLK |
| q | Q |
| qn | Qn |
Typical values
Supply voltage: 3.3 V or 5 V (CMOS). Maximum clock frequency: 100 MHz to several GHz (technology-dependent). Propagation delay (tpd): 1–10 ns. Setup time (tsu): 1–5 ns. Hold time (th): 0.5–2 ns. T input: logic HIGH (1) enables toggle; logic LOW (0) disables toggle. Output: Q (0 or 1), Qn (complement of Q). Designator: FF or Q.
Where the T Flip-Flop symbol is used
- Divide-by-2 frequency dividers in clock generation circuits and PLL output dividers
- Binary ripple counters (cascaded T flip-flops dividing clock by 2^N)
- Synchronous binary counters as the basic toggle cell in each bit position
- Frequency synthesiser prescalers halving a high-frequency VCO output
- Digital clock circuits generating seconds, minutes, and hours from a crystal oscillator
- PWM period generators dividing a master clock to produce lower-frequency PWM base clocks
- State machine implementations where a bit must toggle between two states on each trigger event
Example
In a four-bit binary ripple counter circuit diagram, four T Flip-Flop symbols are cascaded: each flip-flop has its T input tied to logic HIGH (1) and its Qn output connected to the CLK input of the next flip-flop. A 16 MHz input clock applied to the CLK of the first T flip-flop produces 8 MHz at Q of FF1, 4 MHz at Q of FF2, 2 MHz at Q of FF3, and 1 MHz at Q of FF4, counting 0–15 in binary and dividing the input clock by 16.
Key facts
- The T Flip-Flop (Toggle flip-flop) toggles its Q output on each active clock edge when T = 1, and holds Q unchanged when T = 0; the Qn output is always the complement of Q.
- The symbol is a rectangle with T and CLK inputs on the left and Q and Qn outputs on the right; the CLK terminal has an edge-trigger triangle indicator per IEC 60617-12 and IEEE 91A / ANSI Y32.14.
- A T flip-flop with T permanently held HIGH (T = 1) divides the input clock frequency by exactly 2, producing Q at f/2 — the fundamental divide-by-2 building block.
- Cascading N T flip-flops in series (each Qn to next CLK) creates a binary ripple counter dividing the input clock by 2^N and counting pulses from 0 to 2^N − 1.
- The T flip-flop truth table has only two rows: T=0 (Q stays unchanged, Q_next = Q_prev), and T=1 (Q toggles, Q_next = NOT Q_prev); triggered on the clock edge.
- A T flip-flop can be derived from a JK flip-flop by tying the J and K inputs together (J=K=T); it can also be derived from a D flip-flop by connecting Qn back to the D input through an XOR gate with the T input.
- Setup time (tsu) and hold time (th) constraints at the T and CLK inputs must be met to ensure reliable toggling; violating these causes metastability — an indeterminate output state.
Frequently asked questions
What does the T flip-flop symbol mean in a circuit diagram?
The T Flip-Flop symbol represents a clocked toggle flip-flop that changes its output state (Q) on each active clock edge when the T input is HIGH, and holds its state when T is LOW. It is a 1-bit memory element used to divide frequencies by 2 and build binary counters. The Q and Qn outputs are always complementary.
What does the T flip-flop symbol look like?
The T flip-flop symbol is a rectangle with the T (Toggle) input and CLK (Clock) input on the left side and Q and Qn outputs on the right side. The CLK input has a small triangle (edge-trigger indicator) drawn at the input pin inside the rectangle, indicating edge-triggered operation. This is the standard IEC 60617-12 and IEEE 91A rectangular logic block format.
How does a T flip-flop differ from a D flip-flop?
A D flip-flop (Data flip-flop) captures whatever logic level is present at the D input on each clock edge and stores it as Q. A T flip-flop does not store an external data value — instead, it either toggles Q (if T=1) or holds Q (if T=0) on each clock edge. A D flip-flop can implement any sequential function; a T flip-flop is specialised for counting and frequency division.
What is a T flip-flop used for?
T flip-flops are primarily used as frequency dividers (Q toggles at half the clock frequency when T=1) and as the toggle element in binary counters. Each T flip-flop divides the clock frequency by 2; cascading N flip-flops divides by 2^N. They are also used in state machines requiring a bit to toggle between two states on each trigger event.
What standard defines the T flip-flop symbol?
The T flip-flop symbol is defined in IEC 60617-12 (binary logic elements) and IEEE 91A / ANSI Y32.14 (graphic symbols for logic functions). Both use the same rectangular block symbol with T and CLK inputs on the left and Q and Qn outputs on the right, with an edge-trigger triangle at the CLK terminal.
What is the T flip-flop truth table?
The T flip-flop has a simple truth table: when T = 0 at the active clock edge, Q_next = Q_prev (no change); when T = 1 at the active clock edge, Q_next = NOT Q_prev (toggle). The Qn output always equals NOT Q. The flip-flop is only affected at the clock edge (rising or falling, depending on design) — not during the clock level.
How is a T flip-flop made from a JK flip-flop?
A T flip-flop is created from a JK flip-flop by tying the J and K inputs together and using that combined input as the T input. When T=J=K=0, the JK flip-flop holds (Q unchanged). When T=J=K=1, the JK flip-flop toggles (Q inverts). This is because the JK flip-flop's toggle mode (J=K=1) exactly implements the T flip-flop's T=1 behaviour.
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