Tri-State Buffer Symbol
Definition: The Tri-State Buffer symbol represents a digital logic gate that drives its output to logic HIGH, logic LOW, or a high-impedance (Hi-Z) floating state under control of an Enable (EN) input, as defined in IEEE 315 / ANSI Y32.2 and IEC 60617-12, with three terminals: In (data input), Out (data output), and EN (enable control).
Also known as: three-state buffer, 3-state buffer, tristate driver, bus driver, Hi-Z buffer, three-state gate.
What the Tri-State Buffer symbol means
The Tri-State Buffer symbol represents a logic gate with three possible output states: HIGH (logic 1), LOW (logic 0), and high-impedance (Hi-Z), where the Hi-Z state effectively disconnects the output from the bus as if no device were connected. This third state is controlled by the Enable (EN) pin — when EN is asserted, the buffer drives its output according to its input; when EN is deasserted, the output floats to Hi-Z and ceases to load or drive the bus.
In schematic diagrams, the tri-state buffer symbol appears wherever multiple digital devices share a common bus line — such as a microcontroller data bus, an address bus, or an I/O expansion bus. By enabling only one driver at a time, bus contention (two outputs driving opposite logic levels simultaneously) is prevented. Tri-state buffers are fundamental building blocks in CPUs, memory interfaces, and logic ICs such as the 74HC125 and 74HC244.
How to identify the Tri-State Buffer symbol
The Tri-State Buffer symbol is drawn as a standard digital buffer triangle (an equilateral triangle pointing right, with input on the left vertex and output at the right vertex tip), identical to a non-inverting buffer, with one important addition: a short line enters the apex or underside of the triangle to represent the Enable (EN) input. In active-low enable variants, a small circle (inversion bubble) is placed on this EN line before it meets the triangle body. The enable line is typically drawn perpendicular to the main signal path — entering from below or above the triangle rather than from the left side.
Function in a circuit
A tri-state buffer passes its input logic level directly to its output when Enable is asserted, and presents a high-impedance state (Hi-Z) when Enable is deasserted. In the Hi-Z state the output driver transistors are both turned off, so the output pin neither sources nor sinks current and behaves as if it were disconnected from the circuit. This allows many tri-state buffer outputs to be connected in parallel on a shared bus with only one buffer driving at any instant. The buffer also provides electrical buffering: it regenerates signal edges, isolates capacitive bus loads from source devices, and can drive higher fan-out than a standard logic gate output.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 (binary logic elements): the tri-state buffer is drawn as a rectangle with a qualifying symbol (a triangle for high-impedance output capability) and an enable input; the label 'EN' or 'E' marks the enable pin. |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2 / IEEE 315 and IEEE 91 (logic symbols): the distinctive triangular buffer body is used with an additional EN control line entering the triangle. IEEE 91a-1991 specifies the three-state output using an open-collector/tri-state qualifier symbol. Designator: U or BUF. |
| Key difference | IEC 60617-12 favours rectangular logic symbols with qualifying labels; ANSI/IEEE 91 uses the triangular buffer shape. Both convey the same function. The triangular form is far more common in practice, especially in US and international digital circuit documentation. |
Terminals / pins
| Pin | Name |
|---|---|
| in | In |
| out | Out |
| en | EN |
Typical values
Logic family examples: 74HC125 (quad tri-state buffer, active-low EN, VCC 2–6 V, IOL/IOH ±25 mA); 74HC244 (octal tri-state buffer/line driver, VCC 2–6 V); 74LVTH16244 (16-bit, 3.3 V bus driver). Propagation delay: 5–15 ns for HC family at 5 V. Hi-Z output leakage: typically <1 µA.
Where the Tri-State Buffer symbol is used
- Microprocessor and microcontroller data bus and address bus isolation circuits
- Shared memory bus arbitration in multi-master systems (CPU + DMA controller)
- Bidirectional level-shifting bus interfaces where direction is controlled by EN
- I/O port expansion using 74HC244 or similar octal bus drivers
- FPGA output enable control for configuring pin direction at run time
- Multiplexed display bus drivers where only one row/column driver is active at a time
Example
In an 8-bit parallel memory interface, four 74HC125 quad tri-state buffers connect eight memory chips' data outputs to the CPU data bus. Each memory chip's buffer enable is driven by its chip-select decoder output — only the selected chip's buffer drives the bus while all others remain in Hi-Z, preventing bus contention and allowing the CPU to read the correct data byte.
Key facts
- The Tri-State Buffer symbol is a right-pointing triangle (ANSI/IEEE) or rectangle (IEC) with a standard buffer function, plus an Enable (EN) control input line entering the triangle body from below or above.
- Three output states: HIGH (logic 1), LOW (logic 0), and Hi-Z (high impedance, effectively disconnected); the EN pin selects between driven and Hi-Z modes.
- Terminal designators: In (data input), Out (data output), EN (enable, active-high or active-low); reference designator U (or BUF) per IEEE 315.
- Active-low enable variants show a small inversion bubble on the EN lead before it enters the triangle body — the bubble means EN must be LOW to activate the buffer.
- IEC 60617-12 uses a rectangular logic symbol; IEEE 91 / ANSI Y32.2 uses the triangular buffer symbol — both represent the same three-state function.
- Common ICs: 74HC125 (quad, active-low EN), 74HC244 (octal, two active-low enable groups), 74HC373 (octal latch with tri-state output).
- Multiple tri-state buffer outputs may be wired OR (bus connected) provided only one enable is asserted at any time — simultaneous assertion causes bus contention and possible IC damage.
- Hi-Z leakage current is typically less than 1 µA, making the output effectively invisible to the bus during the disabled state.
Frequently asked questions
What does the tri-state buffer symbol look like?
The tri-state buffer symbol looks like a standard logic buffer — a right-pointing equilateral triangle with the data input on the left and output on the right — with an additional Enable (EN) control line entering the body of the triangle from below (or above). If the enable is active-low, a small circle (inversion bubble) appears on the EN line just before it meets the triangle.
What does the tri-state buffer symbol mean in a circuit?
The tri-state buffer symbol means that output can be in one of three states: HIGH, LOW, or high-impedance (Hi-Z). When the Enable input is asserted, the buffer drives its output HIGH or LOW according to its data input. When Enable is deasserted, the output floats to Hi-Z — effectively disconnecting the device from the bus so other drivers can use it.
What is the difference between a buffer and a tri-state buffer symbol?
A standard (two-state) buffer symbol is a plain triangle with input and output only — it always drives its output. The tri-state buffer symbol adds a third Enable (EN) control line to the triangle, giving the output a third Hi-Z state. Without this EN line, the device cannot release the bus.
What does Hi-Z mean on a tri-state buffer?
Hi-Z stands for high impedance. When a tri-state buffer is disabled (EN deasserted), both the output pull-up and pull-down transistors are turned off, leaving the output pin floating with very high resistance (leakage typically below 1 µA). To the bus, the pin appears absent — it neither drives HIGH nor LOW.
What is the designator letter for a tri-state buffer?
The reference designator is U (integrated circuit / logic element) per IEEE 315 / ANSI Y32.2. Some schematics label it BUF or add a functional suffix such as U1A for the first gate in a quad package. IEC schematics may use the same U prefix.
What is the IEC vs ANSI difference for the tri-state buffer symbol?
ANSI / IEEE 91 uses a right-pointing triangle for the buffer body with an EN line entering the triangle side. IEC 60617-12 uses a rectangular logic symbol with a qualifying internal label for high-impedance output capability. In practice, the triangular ANSI/IEEE form is used in almost all digital schematic tools worldwide, including European ones.
What standard defines the tri-state buffer symbol?
The tri-state buffer symbol is defined in IEEE 91-1984 / IEEE 91a-1991 (graphic symbols for logic functions), which is incorporated by reference in ANSI Y32.2, and in IEC 60617-12 (binary logic elements). Both standards specify the enable-controlled three-state output function.
Why are tri-state buffers used on shared buses?
Tri-state buffers allow multiple devices to share a single bus without fighting each other: each device's output is connected through its own tri-state buffer, and a bus controller asserts only one buffer's Enable at a time. The inactive buffers present Hi-Z to the bus, preventing bus contention — the condition where two outputs try to drive opposite logic levels, which can damage ICs and corrupt data.
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