NAND Gate Symbol

The NAND Gate schematic symbol. Standard-specific details are listed below where available.

Definition: The NAND Gate symbol represents a universal logic gate that produces a LOW (0) output only when all of its inputs (A and B) are simultaneously HIGH (1), and a HIGH (1) output for all other input combinations, depicted in ANSI/IEEE 91-1984 as a D-shape (AND body) with a bubble at the output, and in IEC 60617-12 as a rectangle with the qualifying symbol '&' inside followed by a negation circle at the output.

Also known as: NAND, not-AND gate, universal gate, Sheffer stroke gate, 74HC00, 74LS00.

What the NAND Gate symbol means

The NAND Gate symbol represents the logical complement of the AND function: the output is HIGH unless ALL inputs are simultaneously HIGH. The NAND gate is called a 'universal gate' because any other Boolean logic function (AND, OR, NOT, NOR, XOR) can be constructed using only NAND gates. This makes NAND gates the most widely used building block in digital integrated circuit design.

In a schematic, the NAND gate symbol communicates that the block performs a negative-AND operation on its inputs A and B, producing output Out = NOT(A AND B) = A̅·B̅ (per De Morgan's theorem, equivalently = Ā + B̄). The bubble on the output terminal is the critical visual identifier that distinguishes the NAND gate from the AND gate.

How to identify the NAND Gate symbol

The NAND Gate symbol in ANSI/IEEE 91-1984 is drawn as a D-shape: a flat back (left side) with a curved front (right side, like a D), with a small circle (bubble) at the output terminal on the right. Two input lines (A and B) enter from the left flat edge; the output Out exits from the right after the bubble. The IEC 60617-12 symbol is a rectangle with '&' inside and a negation circle (small circle) at the output. The bubble at the output is the universal indicator of logical negation on the gate output.

Function and usage boundary

The NAND gate computes the logical function Out = NOT(A AND B). Its truth table: A=0,B=0 → Out=1; A=0,B=1 → Out=1; A=1,B=0 → Out=1; A=1,B=1 → Out=0. The NAND gate is implemented in CMOS as two series NMOS pull-down transistors and two parallel PMOS pull-up transistors. It is a universal gate: two NAND gates can make a NOT (tie inputs); four NAND gates make an OR gate; two NAND-as-NOTs plus one NAND make an AND. NAND-based design minimises transistor count in CMOS processes.

Standards: IEC vs ANSI

IEC 60617	IEC 60617-12 defines the NAND gate as a rectangle with '&' (AND qualifying symbol) inside and a negation indicator (small circle or slash) at the output terminal. The standard number is IEC 60617-12 (binary logic elements).
ANSI/IEEE 315	ANSI/IEEE 91-1984 (IEEE Standard for Logic Symbols for Digital Logic) uses the distinctive-shape symbol: a curved D-body (AND shape) with a bubble (small circle) at the output. This is the most recognisable NAND gate shape in US and many international textbooks.
Key difference	IEC 60617-12 uses a rectangle with '&' inside plus output bubble; ANSI/IEEE 91-1984 uses a D-shaped AND body plus output bubble. Both carry the same input (A, B) and output (Out) terminals and represent the identical logical function NOT(A·B).

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Logical terminals

Logical ID	Editor terminal name
a	A
b	B
out	Out

Where the NAND Gate symbol is used

Universal logic implementation: any Boolean function is realisable using only NAND gates, making NAND the preferred gate in custom IC design for circuit minimisation
SR latch construction: two cross-coupled NAND gates form a basic SR latch (set-reset bistable memory element)
Clock and control logic: NAND gates generate active-low enable, clock-inhibit, and chip-select signals in microprocessor bus circuits
Oscillator circuits: a NAND gate with feedback and an RC network forms a simple relaxation oscillator
Address decoding: NAND gates combine address lines to generate chip-select (CS̅) signals in memory interface circuits
Digital comparators and arithmetic units: NAND gate arrays implement full-adder and comparator logic in ALU building blocks

Key facts

The NAND gate symbol represents the logical function NOT(A AND B): output is LOW only when all inputs are HIGH simultaneously.
ANSI/IEEE 91-1984 uses a D-shaped AND body with a bubble at the output; IEC 60617-12 uses a rectangle with '&' and a negation circle at the output.
The NAND gate is a universal gate: any Boolean logic function can be implemented using only NAND gates, with no other gate types needed.
Truth table: (0,0)→1; (0,1)→1; (1,0)→1; (1,1)→0 — only one output is LOW (when both inputs are HIGH).
The 74HC00 contains four independent 2-input NAND gates in a 14-pin package; the 74HC10 contains three 3-input NAND gates; the 74HC20 contains two 4-input NAND gates.
De Morgan's theorem: NOT(A AND B) = (NOT A) OR (NOT B) — a NAND gate is equivalent to an OR gate with inverted inputs, which is the basis for bubble-pushing in logic simplification.
In CMOS technology, the NAND gate has a natural advantage over the NOR gate: series NMOS transistors (NAND pull-down network) are faster than series PMOS (NOR pull-up), making NAND the preferred gate in standard-cell libraries.

Frequently asked questions

What does the NAND gate symbol mean in a circuit diagram?

The NAND gate symbol means the block outputs HIGH for all input combinations except when all inputs are simultaneously HIGH, in which case the output is LOW. The function is NOT(A AND B), and the bubble on the output indicates the inversion of the AND operation.

What does the NAND gate symbol look like?

In ANSI/IEEE 91-1984, the NAND gate symbol is a D-shaped body (like an AND gate) with a small circle (bubble) at the output terminal. In IEC 60617-12, it is a rectangle with '&' inside and a small negation circle at the output. The bubble is the key feature that distinguishes NAND from AND.

What is the truth table for a NAND gate?

The 2-input NAND gate truth table: A=0,B=0 → Out=1; A=0,B=1 → Out=1; A=1,B=0 → Out=1; A=1,B=1 → Out=0. The output is 0 only when both A and B are 1; all other input combinations produce output 1.

Why is the NAND gate called a universal gate?

The NAND gate is called a universal gate because every other Boolean logic function — AND, OR, NOT, NOR, XOR, XNOR — can be built using only NAND gates. A single NAND with tied inputs acts as a NOT; two NAND-inverters plus one NAND make an AND; four NANDs can make an OR gate.

What is the difference between a NAND gate and an AND gate symbol?

The AND gate symbol (ANSI/IEEE) is a D-shape without any output bubble; the output is HIGH only when all inputs are HIGH. The NAND gate symbol is identical but adds a small circle (bubble) at the output, indicating the output is inverted — LOW only when all inputs are HIGH.

What IEC standard defines the NAND gate symbol?

The NAND gate symbol is defined in IEC 60617-12 (binary logic elements). The ANSI/IEEE equivalent standard is ANSI/IEEE 91-1984 (IEEE Standard for Logic Symbols for Digital Logic). Both define the same logic function NOT(A AND B) with different visual representations.

What common IC contains NAND gates?

The 74HC00 (CMOS) and 74LS00 (TTL) are quad 2-input NAND gate ICs in 14-pin packages, each containing four independent NAND gates. The 74HC10 contains three 3-input NAND gates; the 74HC20 contains two 4-input NAND gates. All are represented by the NAND gate symbol.

Related symbols

Physical breadboard, PCB, and panel mapping

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