NOT Gate / Inverter Symbol
Definition: The NOT Gate / Inverter symbol represents a single-input, single-output digital logic gate whose output is always the logical complement of its input — HIGH when the input is LOW and LOW when the input is HIGH — defined in IEC 60617-12 (rectangular body with '1' qualifier and output negation indicator) and ANSI Y32.2 / IEEE 315 (triangular body with an inversion bubble at the output).
Also known as: inverter, logic inverter, NOT gate, buffer inverter, logical NOT, complement gate.
What the NOT Gate / Inverter symbol means
The NOT Gate / Inverter symbol denotes the simplest combinational logic element: it performs Boolean negation, outputting the complement of the input signal. If the input In is logic HIGH (1), the output Out is logic LOW (0); if In is LOW (0), Out is HIGH (1). This operation is written Y = NOT A = Ā.
In circuit schematics the NOT Gate symbol conveys that the signal is inverted at this point in the logic chain. Inverters are ubiquitous in digital design: they restore logic levels in long signal paths, create complementary signals for push-pull drivers, and form the basis of ring oscillators, RS latches, and clock buffers. The symbol has one input pin (In) and one output pin (Out).
How to identify the NOT Gate / Inverter symbol
In the ANSI/IEEE distinctive-shape convention (ANSI Y32.2 / IEEE 315), the NOT Gate symbol is a triangle pointing to the right with a small circle (inversion bubble) at the apex (output) tip. The input connects to the flat left side of the triangle. In the IEC rectangular-body convention (IEC 60617-12), it is a rectangle with the qualifying function symbol '1' inside and a negation indicator (circle or horizontal line with bar) at the output. The single-input, single-output triangular shape with an output bubble is the most widely recognised inverter symbol worldwide.
Function in a circuit
The NOT Gate inverts the logic state of its single input. In CMOS technology a NOT gate is implemented as a complementary pair of one PMOS and one NMOS transistor sharing gate and drain connections: when the input is HIGH the NMOS conducts and pulls the output LOW; when the input is LOW the PMOS conducts and pulls the output HIGH. This gives rail-to-rail output swing, near-zero static power consumption, and a sharp voltage transfer characteristic (VTC). Propagation delay is typically 3–10 ns in standard CMOS logic families.
Standards: IEC vs ANSI
| IEC 60617 | IEC 60617-12 defines the NOT gate symbol as a rectangle with the qualifying function label '1' (indicating a single-input buffer/inverter threshold) and a negation indicator at the output, per the IEC general logic symbol convention. |
|---|---|
| ANSI/IEEE 315 | ANSI Y32.2-1975 (reaffirmed 1989) and IEEE 315-1975 define the NOT gate as a right-pointing triangle with a small inversion bubble at the output tip. This is the predominant symbol in North American datasheets, textbooks, and EDA tools. |
| Key difference | The ANSI/IEEE NOT gate uses a distinctive triangle-plus-bubble shape. The IEC NOT gate uses a rectangle with '1' qualifier and output negation indicator. Both represent Y = NOT A but are visually quite different; the ANSI shape is more intuitive for quick schematic reading. |
Terminals / pins
| Pin | Name |
|---|---|
| in | In |
| out | Out |
Typical values
Logic levels (5 V CMOS): LOW = 0–1.5 V in, HIGH = 3.5–5 V in. Propagation delay (tpd): 3–10 ns for 74HC04 at 5 V. Supply voltage: 2–6 V (74HCxx), 1.65–5.5 V (74AHCxx), 0.8–3.6 V (74VCxx). Drive capability (74HC04): IOH = −4 mA (HIGH), IOL = +4 mA (LOW). Common ICs: 74HC04 (hex inverter), CD4069 (hex unbuffered inverter), 74HCT04 (TTL-compatible input).
Where the NOT Gate / Inverter symbol is used
- Signal complementing: generating the inverted clock or control signal needed for differential logic pairs (e.g., CLK and CLK̄)
- Level restoration: buffering long signal traces to regenerate sharp logic edges before fan-out to multiple inputs
- Ring oscillator: an odd number of inverters (typically 3, 5, or 7) connected in a ring produce a self-sustaining square wave for on-chip timing calibration
- SR latch from NAND/NOR: inverters convert active-LOW SET and RESET signals to active-HIGH inputs for cross-coupled NAND-gate latches
- Crystal oscillator circuits: an unbuffered CMOS inverter (CD4069) biased into its linear region acts as a single-stage amplifier for a quartz crystal feedback loop
- Power-on reset (POR) circuits: an inverter with an RC network on its input generates a delayed reset pulse at power-up
Example
In a 32 kHz crystal oscillator, an unbuffered CMOS inverter (CD4069 pin 1–2) is biased into its linear region by a 10-MΩ feedback resistor from Out to In. A 32.768 kHz quartz crystal connects between the input and a 22 pF load capacitor to ground. A second inverter buffers the output to provide a clean square wave to the RTC IC clock input, with the two-inverter chain restoring full CMOS swing from the near-sinusoidal oscillator signal.
Key facts
- The NOT Gate performs Boolean negation: output Y = NOT A = Ā; the output is always the logical complement of the input.
- In the ANSI/IEEE distinctive-shape symbol the NOT gate is a right-pointing triangle with a small inversion bubble at the output; in IEC 60617-12 it is a rectangle with a '1' qualifier and an output negation indicator.
- A CMOS NOT gate is implemented with one PMOS and one NMOS transistor; it has near-zero static power dissipation because at steady state only one transistor conducts at any time.
- The NOT gate is the simplest logic gate: it has one input pin (In) and one output pin (Out), and its truth table has only two rows: 0→1 and 1→0.
- An odd number of inverters connected in a ring forms a ring oscillator; three inverters with propagation delay tpd each produce a square wave at frequency f ≈ 1/(6·tpd).
- 74HC04 is a widely used hex inverter IC containing six independent NOT gates in a 14-pin DIP or SOIC package, operating from 2–6 V.
- An unbuffered inverter (CD4069UB) biased linearly acts as a single-stage high-gain amplifier suitable for crystal oscillator circuits; a standard buffered inverter (CD4069) should not be used in the linear region because it has three cascaded inverter stages.
Frequently asked questions
What does the NOT gate symbol mean in a circuit diagram?
The NOT Gate symbol represents a digital logic inverter: it produces an output that is always the logical complement of its input. If the input is HIGH (1), the output is LOW (0), and vice versa. It is defined in IEC 60617-12 and ANSI Y32.2 / IEEE 315.
What does the NOT gate / inverter symbol look like?
In ANSI/IEEE notation the NOT Gate symbol is a right-pointing triangle with a small inversion bubble (circle) at the output tip. In IEC notation it is a rectangle with the qualifier '1' and a negation indicator at the output. The input connects to the left (flat) side of the triangle or rectangle.
What is the difference between an ANSI NOT gate and an IEC inverter symbol?
The ANSI/IEEE NOT gate uses a triangle-plus-bubble shape; the IEC NOT gate uses a rectangle with a '1' qualifier and an output negation indicator. Both represent the same Boolean function Y = NOT A, but ANSI uses a distinctive shape while IEC uses a uniform rectangular body for all gate types.
What is the truth table of a NOT gate?
The NOT gate truth table has two rows: input A = 0 gives output Y = 1; input A = 1 gives output Y = 0. The output is always the logical complement of the input.
What is the designator for a NOT gate on a schematic?
Logic gates are typically designated with 'U' (U1, U2, etc.) on a schematic, followed by the gate letter within an IC package (U1A, U1B). The 74HC04 hex inverter IC, for example, would appear as U1 containing inverters U1A through U1F.
How is a NOT gate implemented in CMOS?
A CMOS NOT gate uses one PMOS transistor (source to VDD, drain to output) and one NMOS transistor (source to GND, drain to output) with both gates tied together as the input. When the input is HIGH, NMOS conducts and pulls the output LOW; when LOW, PMOS conducts and pulls the output HIGH. At steady state only one transistor conducts, giving near-zero static power.
Can a NOT gate be used as a crystal oscillator amplifier?
Yes. An unbuffered CMOS inverter (such as the CD4069UBE) can be used as a crystal oscillator amplifier by adding a high-value feedback resistor (1–10 MΩ) from output to input, which biases the inverter into its linear region as a single-stage amplifier. A quartz crystal and two small load capacitors (12–22 pF) complete the Pierce oscillator circuit.
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